Soumya Mahapatra

Orcid: 0009-0003-3737-6132

According to our database1, Soumya Mahapatra authored at least 6 papers between 2021 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
11.2 A Blocker-Tolerant Receiver with VCO-Based Non-Uniform Multi-Level Time-Approximation Filter with -36dB EVM in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

26.1: A 24GHz Direct Digital Transmitter Using Multiphase Subharmonic Switching PA Achieving 3.2Gb/s Data Rate and -30.8dB EVM in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024
A Blocker-Tolerant Non-Uniform Sub-Sampling Receiver With a Non-Uniform Discrete-Time FIR Filter.
IEEE J. Solid State Circuits, December, 2024

5.3 A 0.072mm<sup>2</sup> 18-to-21GHz Non-Uniform Sub-Sampling Receiver with a Non-Uniform Discrete-Time FIR Filter Achieving 42dB Blocker Rejection in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2021
A 24-28 GHz Concurrent Harmonic and Subharmonic Tuning Class E/F2, 2/3 Subharmonic Switching Power Amplifier Achieving Peak/PBO Efficiency Enhancement.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021


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