Srikar Vanavasam

Orcid: 0000-0002-4224-2812

According to our database1, Srikar Vanavasam authored at least 5 papers between 2023 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2025
HINT: A Hardware Platform for Intra-Host NIC Traffic and SmartNIC Emulation.
IEEE Comput. Archit. Lett., 2025

Dynamic Load Balancer in Intel Xeon Scalable Processor: Performance Analyses, Enhancements, and Guidelines.
Proceedings of the 52nd Annual International Symposium on Computer Architecture, 2025

2024
Demystifying a CXL Type-2 Device: A Heterogeneous Cooperative Computing Perspective.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

HAL: Hardware-assisted Load Balancing for Energy-efficient SNIC-Host Cooperative Computing.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

2023
Turbo: SmartNIC-enabled Dynamic Load Balancing of µs-scale RPCs.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023


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