Srikar Vanavasam

According to our database, Srikar Vanavasam authored at least 6 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

CXL-Tracer: Accurate, Full-System Memory Tracing on Commercial Hardware via CXL Memory.

Srikar Vanavasam, Austin Antony Cruz, Nam Sung Kim

IEEE Comput. Archit. Lett., 2026

2025

HINT: A Hardware Platform for Intra-Host NIC Traffic and SmartNIC Emulation.

Jiaqi Lou, Yu Li, Srikar Vanavasam, Nam Sung Kim

IEEE Comput. Archit. Lett., 2025

Dynamic Load Balancer in Intel Xeon Scalable Processor: Performance Analyses, Enhancements, and Guidelines.

Jiaqi Lou, Srikar Vanavasam, Yifan Yuan, Ren Wang, Nam Sung Kim

Proceedings of the 52nd Annual International Symposium on Computer Architecture, 2025

2024

Demystifying a CXL Type-2 Device: A Heterogeneous Cooperative Computing Perspective.

Houxiang Ji, Srikar Vanavasam, Yang Zhou, Qirong Xia, Jinghan Huang, Yifan Yuan, Ren Wang, Pekon Gupta, Bhushan Chitlur, Ipoom Jeong, Nam Sung Kim

Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

HAL: Hardware-assisted Load Balancing for Energy-efficient SNIC-Host Cooperative Computing.

Jinghan Huang, Jiaqi Lou, Srikar Vanavasam, Xinhao Kong, Houxiang Ji, Ipoom Jeong, Danyang Zhuo, Eun Kyung Lee, Nam Sung Kim

Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

2023

Turbo: SmartNIC-enabled Dynamic Load Balancing of µs-scale RPCs.

Hamed Seyedroudbari, Srikar Vanavasam, Alexandros Daglis

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023