Srilata Raman

According to our database1, Srilata Raman authored at least 12 papers between 1989 and 1997.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

1997
Optimization Via Evolutionary Processes.
Adv. Comput., 1997

CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation.
VLSI Design, 1996

Performance-driven MCM partitioning through an adaptive genetic algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 1996

A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
A genetic algorithm-based circuit partitioner for MCMs.
Microprocess. Microprogramming, 1995

1994
A Parallel Simulated Annealing-Based Channel Router.
Int. J. High Speed Comput., 1994

A delay driven FPGA placement algorithm.
Proceedings of the Proceedings EURO-DAC'94, 1994

1991
Quality-time tradeoffs in simulated annealing for VLSI placement.
Proceedings of the Fifteenth Annual International Computer Software and Applications Conference, 1991

1990
Parallel Implementation of Circuit Simulation.
Int. J. High Speed Comput., 1990

An Annealing-Based Circuit Partitioner for Hypercube Architecture: Design and Performance Evaluation.
Int. J. High Speed Comput., 1990

1989
Hirecs: Hypercube Implementation of Relaxation-Based Circuit Simulation.
Int. J. High Speed Comput., 1989


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