Larry G. Jones

According to our database, Larry G. Jones authored at least 16 papers between 1986 and 1997.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

1997

Fast power loss calculation for digital static CMOS circuits.

Sergey Gavrilov, Alexey Glebov, S. Rusakov, David T. Blaauw, Larry G. Jones, Gopalakrishnan Vijayan

Proceedings of the European Design and Test Conference, 1997

CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries.

Mohankumar Guruswamy, Robert L. Maziasz, Daniel Dulitz, Srilata Raman, Venkat Chiluvuri, Andrea Fernandez, Larry G. Jones

Proceedings of the 34st Conference on Design Automation, 1997

1996

Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation.

Srilata Raman, C. L. Liu, Larry G. Jones

VLSI Design, 1996

A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs.

Srilata Raman, C. L. Liu, Larry G. Jones

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Transistor reordering for low power CMOS gates using an SP-BDD representation.

Alexey Glebov, David T. Blaauw, Larry G. Jones

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

1994

A cache-based method for accelerating switch-level simulation.

Larry G. Jones, David T. Blaauw

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

A delay driven FPGA placement algorithm.

Srilata Raman, C. L. Liu, Larry G. Jones

Proceedings of the Proceedings EURO-DAC'94, 1994

1992

An incremental zero/integer delay switch-level simulation environment.

Larry G. Jones

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Zero Delay versus Positive Delay in an Incremental Switch-Level Simulator.

Larry G. Jones

Proceedings of the 29th Design Automation Conference, 1992

1991

Fast batch incremental netlist compilation hierarchical schematics.

Larry G. Jones

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Incremental switch-level simulation with zero/integer-delay.

Larry G. Jones

Proceedings of the conference on European design automation, 1991

Accelerating Switch-Level Simulation by Function Caching.

Larry G. Jones

Proceedings of the 28th Design Automation Conference, 1991

1990

Efficient Evaluation of Circular Attribute Grammars.

Larry G. Jones

ACM Trans. Program. Lang. Syst., 1990

1989

Fast incremental netlist compilation of hierarchical schematics.

Larry G. Jones

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Fast Online/Offline Netlist Compilation of Hierarchical Schematics.

Larry G. Jones

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1986

Hierarchical VLSI Design Systems Based on Attribute Grammars.

Larry G. Jones, Janos Simon

Proceedings of the Conference Record of the Thirteenth Annual ACM Symposium on Principles of Programming Languages, 1986