Ananta K. Majhi

According to our database, Ananta K. Majhi authored at least 26 papers between 1995 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

NIM-X: A Noise Index Model-Based X-Filling Technique to Overcome the Power Supply Switching Noise Effects on Path Delay Test.

Elif Alpaslan, Bram Kruseman, Ananta K. Majhi, Wilmar M. Heuvelman, Jennifer Dworak

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2010

Impact of Temperature on Test Quality.

Lavanya Jagan, Camelia Hora, Bram Kruseman, Stefan Eichenberger, Ananta K. Majhi, V. Kamakoti

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

NIM- a noise index model to estimate delay discrepancies between silicon and simulation.

Elif Alpaslan, Jennifer Dworak, Bram Kruseman, Ananta K. Majhi, Wilmar M. Heuvelman, Paul van de Wiel

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Efficient Grouping of Fail Chips for Volume Yield Diagnostics.

Lavanya Jagan, Ratan Deep Singh, V. Kamakoti, Ananta K. Majhi

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

2008

Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test Quality.

Stefan Eichenberger, Jeroen Geuzebroek, Camelia Hora, Bram Kruseman, Ananta K. Majhi

Proceedings of the 2008 IEEE International Test Conference, 2008

2007

Modeling Power Supply Noise in Delay Testing.

Jing Wang, Duncan M. Hank Walker, Xiang Lu, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul J. A. M. van de Wiel, Stefan Eichenberger

IEEE Des. Test Comput., 2007

Diagnosis of Full Open Defects in Interconnecting Lines.

Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

On Performance Testing with Path Delay Patterns.

Bram Kruseman, Ananta K. Majhi, Guido Gronthoud

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages.

Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects.

Jeroen Geuzebroek, Erik Jan Marinissen, Ananta K. Majhi, Andreas Glowatz, Friedrich Hapke

Proceedings of the 2007 IEEE International Test Conference, 2007

2006

Power Supply Noise in Delay Testing.

Jing Wang, D. M. H. Walker, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul van de Wiel, Stefan Eichenberger

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

A New Algorithm for Dynamic Faults Detection in RAMs.

Mohamed Azimane, Ananta K. Majhi, Guido Gronthoud, Maurice Lousberg

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Memory testing improvements through different stress conditions.

Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen

Proceedings of the 31st European Solid-State Circuits Conference, 2005

Memory Testing Under Different Stress Conditions: An Industrial Evaluation.

Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen

Proceedings of the 2005 Design, 2005

2004

New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders.

Mohamed Azimane, Ananta K. Majhi

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Systematic Defects in Deep Sub-Micron Technologies.

Bram Kruseman, Ananta K. Majhi, Camelia Hora, Stefan Eichenberger, Johan Meirlevede

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

On Hazard-free Patterns for Fine-delay Fault Testing.

Bram Kruseman, Ananta K. Majhi, Guido Gronthoud, Stefan Eichenberger

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003

Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model.

Ananta K. Majhi, Guido Gronthoud, Camelia Hora, Maurice Lousberg, Pop Valer, Stefan Eichenberger

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

2000

Line coverage of path delay faults.

Ananta K. Majhi, V. D. Agrawak, James Jacob, Lalit M. Patnaik

IEEE Trans. Very Large Scale Integr. Syst., 2000

1998

Tutorial: Delay Fault Models and Coverage.

Ananta K. Majhi, Vishwani D. Agrawal

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Mixed-Signal Test.

Ananta K. Majhi, Vishwani D. Agrawal

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Automated AC (Timing) Characterization for Digital Circuit Testing.

S. Balajee, Ananta K. Majhi

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1996

A Novel Path Delay Fault Simulator Using Binary Logic.

Ananta K. Majhi, James Jacob, Lalit M. Patnaik

VLSI Design, 1996

On test coverage of path delay faults.

Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1995

A genetic algorithm-based circuit partitioner for MCMs.

Ananta K. Majhi, Lalit M. Patnaik, Srilata Raman

Microprocess. Microprogramming, 1995

An efficient automatic test generation system for path delay faults in combinational circuits.

Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995