Stefanos Valadimas

According to our database, Stefanos Valadimas authored at least 9 papers between 2010 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Τεχνικές ανίχνευσης και διόρθωσης λαθών χρονισμού για αυξημένη αξιοπιστία ολοκληρωμένων κυκλωμάτων σε νανομετρικές τεχνολογίες

Stefanos Valadimas

PhD thesis, 2016

Timing Error Tolerance in Small Core Designs for SoC Applications.

Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni

IEEE Trans. Computers, 2016

Timing error mitigation in microprocessor cores.

Stefanos Valadimas, Angela Arapoyanni, Yiorgos Tsiatouhas

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2014

The Time Dilation Technique for Timing Error Tolerance.

Stefanos Valadimas, Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Xrysovalantis Kavousianos

IEEE Trans. Computers, 2014

Timing Error Tolerance in Pipeline Based Core Designs.

Stefanos Valadimas, Angela Arapoyanni

Proceedings of the 18th Panhellenic Conference on Informatics, 2014

2013

Effective Timing Error Tolerance in Flip-Flop Based Core Designs.

Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni, Petros Xarchakos

J. Electron. Test., 2013

2012

Cost and power efficient timing error tolerance in flip-flop based microprocessor cores.

Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni

Proceedings of the 17th IEEE European Test Symposium, 2012

Single event upset tolerance in flip-flop based microprocessor cores.

Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni, Adrian Evans

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2010

Timing error tolerance in nanometer ICs.

Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010