Stuart McCracken

According to our database, Stuart McCracken authored at least 4 papers between 2002 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

24.8 A 12GS/s 9b 16× Time-Interleaved SAR ADC in 16nm FinFET.

Junhua Shen, Wei-Hung Chen, Efram Burlingame, Stephen Weinreich, Michael Elliott, Stuart McCracken, Jack Kenney, Janet Brunsilius, Anil Korkmaz, Enrique Alvarez-Fontecilla, Nevena Rakuljic, Ushma Mehta, Ben Sullivan, Jeremy Scuteri, Bac Binh Luu, Mitchell Nichols, Dara Martin, Richard Sullivan, Daniel DeBolt, Ron Kapusta

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2014

A 6.5Mb/s to 11.3Gb/s continuous-rate clock and data recovery.

Jack Kenney, Terry Chen, Larry DeVito, Declan Dalton, Stuart McCracken, Richard Soenneker, Ward S. Titus, Todd S. Weigandt

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2004

Design for Testability of FPGA Blocks.

Stuart McCracken, Zeljko Zilic

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

2002

FPGA test time reduction through a novel interconnect testing scheme.

Stuart McCracken, Zeljko Zilic

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002