Ron Kapusta

Orcid: 0000-0001-9776-6501

According to our database1, Ron Kapusta authored at least 12 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
Introduction to the Special Issue on the 2023 Symposium on VLSI Circuits.
IEEE J. Solid State Circuits, April, 2024

2018
A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS.
IEEE J. Solid State Circuits, 2018

2016
A 16 bit linear passive-charge-sharing SAR ADC in 55nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

SAR ADCs in parallel [time-interleaved] converter arrays.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
Sampling Circuits That Break the kT/C Thermal Noise Limit.
IEEE J. Solid State Circuits, 2014

2013
A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS.
IEEE J. Solid State Circuits, 2013

A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
Data converter techniques.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2009
A 4-channel 20-to300 Mpixel/s analog front-end with sampled thermal noise below kT/C for digital SLR cameras.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Nyquist rate ADCs.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2006
A 14b 74MS/s CMOS AFE for True High-Definition Camcorders.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006


  Loading...