Ron Kapusta

According to our database, Ron Kapusta authored at least 15 papers between 2006 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A 12b 12GS/s Two-Way Interleaved Pipeline ADC with Integrated Broadband RF VGA in 5nm.

Haiyang Zhu, Larry Singer, Ron Kapusta, Dan Kelly, Tao Pan, Mike Hensley, Scott Bardsley, Christopher Dillon, Daniel Rey-Losada, Kashif M. Sheikh, Chen-Kai Hsu, Zhao Li, Janet Brunsilius, Enrique Alvarez-Fontecilla, Robert Bishop, Paul Wilkins, Hassan L'Bahy, Adalberto Cantoni, Nuo Zhang, Kaung Myat San Oo, Cihan Asci

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2025

Guest Editorial Introduction to the Special Issue on the 2024 Symposium on VLSI Circuits.

Ron Kapusta, Sugako Otani

IEEE J. Solid State Circuits, April, 2025

24.8 A 12GS/s 9b 16× Time-Interleaved SAR ADC in 16nm FinFET.

Junhua Shen, Wei-Hung Chen, Efram Burlingame, Stephen Weinreich, Michael Elliott, Stuart McCracken, Jack Kenney, Janet Brunsilius, Anil Korkmaz, Enrique Alvarez-Fontecilla, Nevena Rakuljic, Ushma Mehta, Ben Sullivan, Jeremy Scuteri, Bac Binh Luu, Mitchell Nichols, Dara Martin, Richard Sullivan, Daniel DeBolt, Ron Kapusta

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024

Introduction to the Special Issue on the 2023 Symposium on VLSI Circuits.

Mototsugu Hamada, Ron Kapusta

IEEE J. Solid State Circuits, April, 2024

2018

A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS.

Junhua Shen, Akira Shikata, Lalinda Fernando, Ned Guthrie, Baozhen Chen, Mark Maddox, Nikhil Mascarenhas, Ron Kapusta, Michael C. W. Coln

IEEE J. Solid State Circuits, 2018

2016

A 16 bit linear passive-charge-sharing SAR ADC in 55nm CMOS.

Mark Maddox, Baozhen Chen, Michael C. W. Coln, Ron Kapusta, Junhua Shen, Lalinda Fernando

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier.

Haiyang Zhu, Ron Kapusta, Yong-Bin Kim

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

SAR ADCs in parallel [time-interleaved] converter arrays.

Ron Kapusta

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2013

A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS.

Ron Kapusta, Junhua Shen, Steven Decker, Hongxing Li, Eitake Ibaragi, Haiyang Zhu

IEEE J. Solid State Circuits, 2013

A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS.

Ron Kapusta, Junhua Shen, Steven Decker, Hongxing Li, Eitake Ibaragi

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Sampling circuits that break the kT/C thermal noise limit.

Ron Kapusta, Haiyang Zhu, Colin Lyden

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

Data converter techniques.

Ron Kapusta, Yuji Nakajima

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2009

A 4-channel 20-to300 Mpixel/s analog front-end with sampled thermal noise below kT/C for digital SLR cameras.

Ronald Kapusta, Hiroto Shinozaki, Eitake Ibaragi, Kevin Ni, Richard Wang, Mark T. Sayuk, Larry Singer, Katsu Nakamura

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Nyquist rate ADCs.

Eric Naviasky, Ron Kapusta

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2006

A 14b 74MS/s CMOS AFE for True High-Definition Camcorders.

Ronald A. Kapusta, Shingo Hatanaka, Steven J. Decker, Jianrong Chen, David Foley, Anthony Wellinger, Murat Ozbas, Dan F. Kelly, Mark T. Sayuk, William G. Schofield, Katsu Nakamura

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006