Subhradip Chakraborty
Orcid: 0009-0005-3325-9099
According to our database1,
Subhradip Chakraborty authored at least 10 papers
between 2024 and 2026.
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Bibliography
2026
GEM3D CIM General Purpose Matrix Computation Using 3D Integrated SRAM eDRAM Hybrid Compute In Memory on Memory Architecture.
CoRR, April, 2026
A Pathway to Near Tissue Computing Through Processing-in-CTIA Pixels for Biomedical Applications.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2026
An Energy Efficient Pulse Accumulator Circuit (PAC) Based Multi-Bit Time Domain Compute in-Memory Architecture.
Proceedings of the 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems, 2026
2025
NVM-in-Cache: Repurposing Commodity 6T SRAM Cache into NVM Analog Processing-in-Memory Engine using a Novel Compute-on-Powerline Scheme.
CoRR, October, 2025
A retina-inspired pathway to real-time motion prediction inside image sensors for extreme-edge intelligence.
Neuromorph. Comput. Eng., 2025
Application Specific Hardware-Algorithm Metric Analysis for Vision based In-Sensor Computing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025
A 1.91 POPS/W Energy-Efficient SRAM Based Signed Multi-Bit Time Domain CIM Architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
Memristor-Assisted Secure SRAM Architectures for Protection Against Data Imprinting Attacks.
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2025
2024
An Energy-Efficient Time Domain Based Compute In-Memory Architecture for Binary Neural Network.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
An Area and Energy-Efficient SRAM Based Time - Domain Compute-In-Memory Architecture For BNN.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024