Dinesh Kushwaha

Orcid: 0000-0003-3446-5909

According to our database1, Dinesh Kushwaha authored at least 6 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Multibit MAC Scheme using Switched Capacitor based 3C Multiplier for Analog Compute In-Memory Architecture.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2016
A 415 nW, 0.8 V, voltage reference circuit using MOSFETs in saturation and sub-threshold regions.
Proceedings of the 11th International Conference on Industrial and Information Systems, 2016


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