Subodh Gupta

According to our database1, Subodh Gupta authored at least 8 papers between 1997 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2009
Clock power reduction for virtex-5 FPGAs.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2007
CAD Techniques for Power Optimization in Virtex-5 FPGAs.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2003
Energy and peak-current per-cycle estimation at RTL.
IEEE Trans. Very Large Scale Integr. Syst., 2003

2000
Power modeling for high-level power estimation.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Analytical models for RTL power estimation of combinational andsequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1999
Energy-per-cycle estimation at RTL.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Power macro-models for DSP blocks with application to high-level synthesis.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

1997
Power Macromodeling for High Level Power Estimation.
Proceedings of the 34st Conference on Design Automation, 1997


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