Jason Helge Anderson

Rami Beidas

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors.

[BibT_eX]

[DOI]

Guanglei Zhou

Mirjana Stojilovic

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Area-Driven FPGA Logic Synthesis Using Reinforcement Learning.

[BibT_eX]

[DOI]

Guanglei Zhou

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code.

[BibT_eX]

[DOI]

George A. Constantinides

IEEE Trans. Computers, 2022

Elastic Multi-Context CGRAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

Modeling and Exploration of Elastic CGRAs.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Streaming Accuracy: Characterizing Early Termination in Stochastic Computing.

[BibT_eX]

[DOI]

Hsuan Hsiao

Joshua San Miguel

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

CGRA Mapping Using Zero-Suppressed Binary Decision Diagrams.

[BibT_eX]

[DOI]

Rami Beidas

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Profiling-Based Control-Flow Reduction in High-Level Synthesis.

[BibT_eX]

[DOI]

Austin Liolli

Proceedings of the International Conference on Field-Programmable Technology, 2021

Post-LUT-Mapping Implementation of General Logic on Carry Chains Via a MIG-Based Circuit Representation.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems.

[BibT_eX]

[DOI]

Xiaoyi Ling

Takahiro Notsu

Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

High-Level Synthesis of Transactional Memory.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Zero Correlation Error: A Metric for Finite-Length Bitstream Independence in Stochastic Computing.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Double-Pumping the Interconnect for Area Reduction in Coarse-Grained Reconfigurable Arrays.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

Power, Performance and Area Consequences of Multi-Context Support in CGRAs.

[BibT_eX]

[DOI]

Vimal Chacko

Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

CGRA-ME: An Open-Source Framework for CGRA Architecture and CAD Research : (Invited Paper).

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020

Optimizing FPGA Logic Block Architectures for Arithmetic.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

2019

ASAP: Automatic Sizing and Partitioning for Dynamic Memory Heaps in High-Level Synthesis.

[BibT_eX]

[DOI]

Nicholas V. Giamblanco

Proceedings of the International Conference on Field-Programmable Technology, 2019

High-Level Synthesis Techniques to Generate Deeply Pipelined Circuits for FPGAs with Registered Routing.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2019

Physical Design Considerations for Synthesizable Standard-Cell-Based FPGAs.

[BibT_eX]

[DOI]

Brett Grady

Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2019

A Dynamic Memory Allocation Library for High-Level Synthesis.

[BibT_eX]

[DOI]

Nicholas V. Giamblanco

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

EASY: Efficient Arbiter SYnthesis from Multi-threaded Code.

[BibT_eX]

[DOI]

George A. Constantinides

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Generic Connectivity-Based CGRA Mapping via Integer Linear Programming.

[BibT_eX]

[DOI]

Matthew J. P. Walker

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Impact of FPGA Architecture on Area and Performance of CGRA Overlays.

[BibT_eX]

[DOI]

Ian Taras

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Thread Weaving: Static Resource Scheduling for Multithreaded High-Level Synthesis.

[BibT_eX]

[DOI]

Hsuan Hsiao

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

XOMA: exclusive on-chip memory architecture for energy-efficient deep learning acceleration.

[BibT_eX]

[DOI]

Hyeon Uk Sim

Jongeun Lee

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

Architecture Exploration of Standard-Cell and FPGA-Overlay CGRAs Using the Open-Source CGRA-ME Framework.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on Physical Design, 2018

Accelerating Memcached on AWS Cloud FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

Compact Area and Performance Modelling for CGRA Architecture Evaluation.

[BibT_eX]

[DOI]

Kuang Ping Niu

Proceedings of the International Conference on Field-Programmable Technology, 2018

FPGA Architecture Enhancements for Efficient BNN Implementation.

[BibT_eX]

[DOI]

Jongeun Lee

Proceedings of the International Conference on Field-Programmable Technology, 2018

Synthesizable Heterogeneous FPGA Fabrics.

[BibT_eX]

[DOI]

Brett Grady

Proceedings of the International Conference on Field-Programmable Technology, 2018

Software-Specified FPGA Accelerators for Elementary Functions.

[BibT_eX]

[DOI]

Jing Chen

Xue Liu

Proceedings of the International Conference on Field-Programmable Technology, 2018

High-Level Synthesis of FPGA Circuits with Multiple Clock Domains.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

Sensei: An area-reduction advisor for FPGA high-level synthesis.

[BibT_eX]

[DOI]

Hsuan Hsiao

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

High-level synthesis of software-customizable floating-point cores.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

An architecture-agnostic integer linear programming approach to CGRA mapping.

[BibT_eX]

[DOI]

S. Alexander Chin

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Leveraging Unused Resources for Energy Optimization of FPGA Interconnect.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

From Pthreads to Multicore Hardware Systems in LegUp High-Level Synthesis for FPGAs.

[BibT_eX]

[DOI]

Jongsok Choi

IEEE Trans. Very Large Scale Integr. Syst., 2017

The First 25 Years of the FPL Conference: Significant Papers.

[BibT_eX]

[DOI]

Philip Heng Wai Leong

ACM Trans. Reconfigurable Technol. Syst., 2017

Microarchitectural Comparison of the MXP and Octavo Soft-Processor FPGA Overlays.

[BibT_eX]

[DOI]

Charles Eric LaForest

ACM Trans. Reconfigurable Technol. Syst., 2017

Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2017

Subleq⊝: An Area-Efficient Two-Instruction-Set Computer.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2017

FPGA-based CNN inference accelerator synthesized from multi-threaded C software.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Automated generation of banked memory architectures in the high-level synthesis of multi-threaded software.

[BibT_eX]

[DOI]

Yu Ting Chen

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

CGRA-ME: A unified framework for CGRA modelling and exploration.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016

Hybrid LUT/Multiplexer FPGA Logic Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

A Survey and Evaluation of FPGA High-Level Synthesis Tools.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Power Optimization of FPGA Interconnect Via Circuit and CAD Techniques.

[BibT_eX]

[DOI]

Proceedings of the 2016 on International Symposium on Physical Design, 2016

High-level synthesis - the right side of history.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Preface.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Towards PVT-Tolerant Glitch-Free Operation in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracy.

[BibT_eX]

[DOI]

Yuko Hara-Azumi

Shigeru Yamashita

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A unified software approach to specify pipeline and spatial parallelism in FPGA hardware.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

LegUp High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the FPGAs for Software Programmers, 2016

2015

The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2015

Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardware.

[BibT_eX]

[DOI]

Jongsok Choi

Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Significant papers from the first 25 years of the FPL conference.

[BibT_eX]

[DOI]

Philip Heng Wai Leong

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Synthesizable-from-C Embedded Processor Based on MIPS-ISA and OISC.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015

Profiling-driven multi-cycling in FPGA high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

VTR 7.0: Next Generation Architecture and CAD System for FPGAs.

[BibT_eX]

[DOI]

Konstantin Nasartschuk

ACM Trans. Reconfigurable Technol. Syst., 2014

Introduction to the Special Issue on the 11<sup>th</sup> International Conference on Field-Programmable Technology (FPT'12).

[BibT_eX]

[DOI]

Kiyoung Choi

ACM Trans. Reconfigurable Technol. Syst., 2014

Approaching overhead-free execution on FPGA soft-processors.

[BibT_eX]

[DOI]

Charles Eric LaForest

J. Gregory Steffan

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Design re-use for compile time reduction in FPGA high-level synthesis flows.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Modulo SDC scheduling with recurrence minimization in high-level synthesis.

[BibT_eX]

[DOI]

Andrew Canis

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Source-level debugging for FPGA high-level synthesis.

[BibT_eX]

[DOI]

Nazanin Calagar

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Towards interconnect-adaptive packing for FPGAs.

[BibT_eX]

[DOI]

Jason Luu

Jonathan Rose

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Optimizing effective interconnect capacitance for FPGA power reduction.

[BibT_eX]

[DOI]

Natalie D. Enright Jerger

Hirotaka Tamura

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

On Hard Adders and Carry Chains in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

Power Modeling for Heterogeneous Processors.

[BibT_eX]

[DOI]

Tahir Diop

Proceedings of the Seventh Workshop on General Purpose Processing Using GPUs, 2014

2013

Combined Architecture/Algorithm Approach to Fast FPGA Routing.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2013

Latch-Based Performance Optimization for Field-Programmable Gate Arrays.

[BibT_eX]

[DOI]

Bill Teng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Leakage power reduction in FPGA DSP circuits through algorithmic noise tolerance.

[BibT_eX]

[DOI]

Edgar Mora-Sanchez

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

DistCL: A Framework for the Distributed Execution of OpenCL Kernels.

[BibT_eX]

[DOI]

Tahir Diop

Steven Gurfinkel

Natalie D. Enright Jerger

Proceedings of the 2013 IEEE 21st International Symposium on Modelling, 2013

Bitwidth-optimized hardware accelerators with software fallback.

[BibT_eX]

[DOI]

Ana Klimovic

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

From software threads to parallel hardware in high-level synthesis for FPGAs.

[BibT_eX]

[DOI]

Jongsok Choi

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

A case for hardened multiplexers in FPGAs.

[BibT_eX]

[DOI]

S. Alexander Chin

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

From C to Blokus Duo with LegUp high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Charge recycling for power reduction in FPGA interconnect.

[BibT_eX]

[DOI]

Hirotaka Tamura

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

High-level synthesis with LegUp: a crash course for users and researchers.

[BibT_eX]

[DOI]

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Multi-pumping for resource reduction in FPGA high-level synthesis.

[BibT_eX]

[DOI]

Andrew Canis

Proceedings of the Design, Automation and Test in Europe, 2013

From software to accelerators with LegUp high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Compilers, 2013

Range and bitmask analysis for hardware optimization in high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Raising FPGA Logic Density Through Synthesis-Inspired Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture.

[BibT_eX]

[DOI]

Andrew A. Kennings

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

FPGA power reduction by guarded evaluation considering physical information.

[BibT_eX]

[DOI]

Andrew A. Kennings

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Analytical placement for heterogeneous FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power.

[BibT_eX]

[DOI]

Warren Wai-Kit Shum

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

The VTR project: architecture and CAD for FPGAs from verilog to routing.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Impact of FPGA architecture on resource sharing in high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Leveraging reconfigurability to raise productivity in FPGA functional debug.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

FPGA glitch power analysis and reduction.

[BibT_eX]

[DOI]

Warren Wai-Kit Shum

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Latch-Based Performance Optimization for FPGAs.

[BibT_eX]

[DOI]

Bill Teng

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Reducing FPGA Router Run-Time through Algorithm and Architecture.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect.

[BibT_eX]

[DOI]

Jason Luu

Jonathan Rose

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

LegUp: high-level synthesis for FPGA-based processor/accelerator systems.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

An integer programming placement approach to FPGA clock power reduction.

[BibT_eX]

[DOI]

Alireza Rakhshanfar

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Area-efficient FPGA logic elements: Architecture and synthesis.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Low-cost hardware profiling of run-time and energy in FPGA embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

2010

Deterministic multi-core parallel routing for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2010

Parallelizing FPGA placement using Transactional Memory.

[BibT_eX]

[DOI]

Steven Birk

J. Gregory Steffan

Proceedings of the International Conference on Field-Programmable Technology, 2010

FPGA power reduction by guarded evaluation.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

A PUF design for secure FPGA-based embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Low-Power Programmable FPGA Routing Circuitry.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Packing Techniques for Virtex-5 FPGAs.

[BibT_eX]

[DOI]

Taneem Ahmed

Paul D. Kundarewich

ACM Trans. Reconfigurable Technol. Syst., 2009

Clock gating architectures for FPGA power reduction.

[BibT_eX]

[DOI]

Muntasir Mallick

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Improving logic density through synthesis-inspired architecture.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Clock power reduction for virtex-5 FPGAs.

[BibT_eX]

[DOI]

Subodh Gupta

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Emerging application domains: research challenges and opportunities for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2008

Architecture-specific packing for virtex-5 FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

2007

CAD Techniques for Power Optimization in Virtex-5 FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Active leakage power optimization for FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2004

Power estimation techniques for FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Low-power programmable routing circuitry for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 2004

Active leakage power optimization for FPGAs.

[BibT_eX]

[DOI]

Tim Tuan

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

A novel low-power FPGA routing switch.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

Interconnect capacitance estimation for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Switching activity analysis and pre-layout activity prediction for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

2002

Power-aware technology mapping for LUT-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

2000

A Placement Algorithm for FPGA Designs with Multiple I/O Standards.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2000

1998

An LPGA with Foldable PLA-style Logic Blocks.

[BibT_eX]

[DOI]

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Technology Mapping for Large Complex PLDs.

[BibT_eX]

[DOI]