Suryanarayana Tatapudi

According to our database1, Suryanarayana Tatapudi authored at least 6 papers between 2003 and 2006.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2006
A mesochronous pipelining scheme for high-performance digital systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

A mesochronous pipeline scheme for high performance low power digital systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Decoupled dynamic ternary content addressable memories.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

A High Performance Hybrid Wave-Pipelined Multiplier.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme.
Proceedings of the 2005 International Conference on Computer Design, 2005

2003
Split-Precharge Differential Noise-Immune Threshold Logic Gate (SPD-NTL).
Proceedings of the Artificial Neural Nets Problem Solving Methods, 2003


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