Sushanta K. Mandal

According to our database, Sushanta K. Mandal authored at least 5 papers between 2005 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

A 6 bit 800MHz TIADC Based on Successive Approximation in 65nm Standard CMOS Process.

Arunkumar Salimath, Chandrajit Debnath, Kallol Chatterjee, Sushanta K. Mandal

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Modelling of Power Distribution Network and Decoupling Network Design for High Speed VLSI Design.

Abhishek Pathak, Sushanta K. Mandal, Raj Kumar Nagpal, Rakesh Malik

Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

2008

ANN- and PSO-Based Synthesis of On-Chip Spiral Inductors for RF ICs.

Sushanta K. Mandal, Shamik Sural, Amit Patra

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2006

A Wide-Band Lumped Element Compact CAD Model of Si-Based Planar Spiral Inductor for RFIC Design.

Sushanta K. Mandal, Arijit De, Amit Patra, Shamik Sural

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2005

A simple wide-band compact model and parameter extraction using particle swarm optimization of on-chip spiral inductors for silicon RFICs.

Sushanta K. Mandal, Arijit De, Amit Patra, Shamik Sural

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005