Swapnil Mhaske

According to our database1, Swapnil Mhaske authored at least 9 papers between 2014 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
A Blockage Model for the Open Area Mm-wave Device-to-Device Environment.
CoRR, 2019

2017
FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis.
Int. J. Reconfigurable Comput., 2017

2016
FPGA-accelerated simulation of a hybrid-ARQ system using high level synthesis.
Proceedings of the 37th IEEE Sarnoff Symposium 2016, Newark, NJ, USA, 2016

Link quality analysis in the presence of blockages for analog beamformed mm-wave channel.
Proceedings of the 2016 IEEE Military Communications Conference, 2016

2015
A 2.48Gb/s QC-LDPC Decoder Implementation on the NI USRP-2953R.
CoRR, 2015

High-Throughput FPGA-Based QC-LDPC Decoder Architecture.
Proceedings of the IEEE 82nd Vehicular Technology Conference, 2015

A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation.
Proceedings of the 36th IEEE Sarnoff Symposium 2015, Newark, NJ, USA, 2015

Rate compatible IRA codes using row splitting for 5G wireless.
Proceedings of the 49th Annual Conference on Information Sciences and Systems, 2015

2014
Rapid and high-level constraint-driven prototyping using lab VIEW FPGA.
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014


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