David Uliana

According to our database, David Uliana authored at least 6 papers between 2013 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2015

A 2.48Gb/s QC-LDPC Decoder Implementation on the NI USRP-2953R.

Swapnil Mhaske, David Uliana, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic

CoRR, 2015

A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation.

Swapnil Mhaske, David Uliana, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic

Proceedings of the 36th IEEE Sarnoff Symposium 2015, Newark, NJ, USA, 2015

2014

FPGA-based accelerator development for non-engineers.

David Uliana, Peter M. Athanas, Krzysztof Kepa

Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Rapid and high-level constraint-driven prototyping using lab VIEW FPGA.

Hojin Kee, Swapnil Mhaske, David Uliana, Adam Arnesen, Newton Petersen, Taylor L. Riché, Dustyn Blasig, Tai Ly

Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014

2013

FPGA-based HPC application design for non-experts.

David Uliana, Krzysztof Kepa, Peter Athanas

Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

FPGA-based HPC application design for non-experts (abstract only).

David Uliana, Krzysztof Kepa, Peter Athanas

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013