Tai Ly

According to our database1, Tai Ly authored at least 9 papers between 1995 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis.
Int. J. Reconfigurable Comput., 2017

2016
FPGA-accelerated simulation of a hybrid-ARQ system using high level synthesis.
Proceedings of the 37th IEEE Sarnoff Symposium 2016, Newark, NJ, USA, 2016

2015
A 2.48Gb/s QC-LDPC Decoder Implementation on the NI USRP-2953R.
CoRR, 2015

High-Throughput FPGA-Based QC-LDPC Decoder Architecture.
Proceedings of the IEEE 82nd Vehicular Technology Conference, 2015

A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation.
Proceedings of the 36th IEEE Sarnoff Symposium 2015, Newark, NJ, USA, 2015

2014
Rapid and high-level constraint-driven prototyping using lab VIEW FPGA.
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014

2009
Scalable and low power LDPC decoder design using high level algorithmic synthesis.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

1995
Scheduling Using Behavioral Templates.
Proceedings of the 32st Conference on Design Automation, 1995

Behavioral Synthesis Methodology for HDL-Based Specification and Validation.
Proceedings of the 32st Conference on Design Automation, 1995


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