Tai Ly

According to our database, Tai Ly authored at least 9 papers between 1995 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis.

Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic

Int. J. Reconfigurable Comput., 2017

2016

FPGA-accelerated simulation of a hybrid-ARQ system using high level synthesis.

Swapnil Mhaske, Hojin Kee, Tai Ly, Predrag Spasojevic

Proceedings of the 37th IEEE Sarnoff Symposium 2016, Newark, NJ, USA, 2016

2015

A 2.48Gb/s QC-LDPC Decoder Implementation on the NI USRP-2953R.

Swapnil Mhaske, David Uliana, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic

CoRR, 2015

High-Throughput FPGA-Based QC-LDPC Decoder Architecture.

Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic

Proceedings of the IEEE 82nd Vehicular Technology Conference, 2015

A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation.

Swapnil Mhaske, David Uliana, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic

Proceedings of the 36th IEEE Sarnoff Symposium 2015, Newark, NJ, USA, 2015

2014

Rapid and high-level constraint-driven prototyping using lab VIEW FPGA.

Hojin Kee, Swapnil Mhaske, David Uliana, Adam Arnesen, Newton Petersen, Taylor L. Riché, Dustyn Blasig, Tai Ly

Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014

2009

Scalable and low power LDPC decoder design using high level algorithmic synthesis.

Yang Sun, Joseph R. Cavallaro, Tai Ly

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

1995

Scheduling Using Behavioral Templates.

Tai Ly, David Knapp, Ron Miller, Don MacMillen

Proceedings of the 32st Conference on Design Automation, 1995

Behavioral Synthesis Methodology for HDL-Based Specification and Validation.

David Knapp, Tai Ly, Don MacMillen, Ron Miller

Proceedings of the 32st Conference on Design Automation, 1995