Hojin Kee

According to our database, Hojin Kee authored at least 14 papers between 2008 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis.

Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic

Int. J. Reconfigurable Comput., 2017

2016

FPGA-accelerated simulation of a hybrid-ARQ system using high level synthesis.

Swapnil Mhaske, Hojin Kee, Tai Ly, Predrag Spasojevic

Proceedings of the 37th IEEE Sarnoff Symposium 2016, Newark, NJ, USA, 2016

2015

A 2.48Gb/s QC-LDPC Decoder Implementation on the NI USRP-2953R.

Swapnil Mhaske, David Uliana, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic

CoRR, 2015

High-Throughput FPGA-Based QC-LDPC Decoder Architecture.

Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic

Proceedings of the IEEE 82nd Vehicular Technology Conference, 2015

A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation.

Swapnil Mhaske, David Uliana, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic

Proceedings of the 36th IEEE Sarnoff Symposium 2015, Newark, NJ, USA, 2015

2014

Rapid and high-level constraint-driven prototyping using lab VIEW FPGA.

Hojin Kee, Swapnil Mhaske, David Uliana, Adam Arnesen, Newton Petersen, Taylor L. Riché, Dustyn Blasig, Tai Ly

Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014

2012

Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware.

Hojin Kee, Chung-Ching Shen, Shuvra S. Bhattacharyya, Ian C. Wong, Yong Rao, Jacob Kornerup

J. Signal Process. Syst., 2012

2011

Topological Patterns for Scalable Representation and Analysis of Dataflow Graphs.

Nimish Sane, Hojin Kee, Gunasekaran S. Seetharaman, Shuvra S. Bhattacharyya

J. Signal Process. Syst., 2011

2010

Systematic Exploration of Trade-Offs between Application Throughput and Hardware Resource Requirements in DSP Systems.

Hojin Kee

PhD thesis, 2010

Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs.

Hojin Kee, Shuvra S. Bhattacharyya, Jacob Kornerup

Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Rapid prototyping for digital signal processing systems using Parameterized Synchronous Dataflow graphs.

Hsiang-Huang Wu, Hojin Kee, Nimish Sane, William Plishker, Shuvra S. Bhattacharyya

Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010

FPGA-based design and implementation of the 3GPP-LTE physical layer using parameterized synchronous dataflow techniques.

Hojin Kee, Shuvra S. Bhattacharyya, Ian C. Wong, Yong Rao

Proceedings of the IEEE International Conference on Acoustics, 2010

2009

Resource-efficient acceleration of 2-dimensional Fast Fourier Transform computations on FPGAs.

Hojin Kee, Shuvra S. Bhattacharyya, Newton Petersen, Jacob Kornerup

Proceedings of the Third ACM/IEEE International Conference on Distributed Smart Cameras, 2009

2008

Systematic generation of FPGA-based FFT implementations.

Hojin Kee, Newton Petersen, Jacob Kornerup, Shuvra S. Bhattacharyya

Proceedings of the IEEE International Conference on Acoustics, 2008