Hojin Kee

According to our database1, Hojin Kee authored at least 14 papers between 2008 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis.
Int. J. Reconfigurable Comput., 2017

2016
FPGA-accelerated simulation of a hybrid-ARQ system using high level synthesis.
Proceedings of the 37th IEEE Sarnoff Symposium 2016, Newark, NJ, USA, 2016

2015
A 2.48Gb/s QC-LDPC Decoder Implementation on the NI USRP-2953R.
CoRR, 2015

High-Throughput FPGA-Based QC-LDPC Decoder Architecture.
Proceedings of the IEEE 82nd Vehicular Technology Conference, 2015

A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation.
Proceedings of the 36th IEEE Sarnoff Symposium 2015, Newark, NJ, USA, 2015

2014
Rapid and high-level constraint-driven prototyping using lab VIEW FPGA.
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014

2012
Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware.
J. Signal Process. Syst., 2012

2011
Topological Patterns for Scalable Representation and Analysis of Dataflow Graphs.
J. Signal Process. Syst., 2011

2010
Systematic Exploration of Trade-Offs between Application Throughput and Hardware Resource Requirements in DSP Systems.
PhD thesis, 2010

Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Rapid prototyping for digital signal processing systems using Parameterized Synchronous Dataflow graphs.
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010

FPGA-based design and implementation of the 3GPP-LTE physical layer using parameterized synchronous dataflow techniques.
Proceedings of the IEEE International Conference on Acoustics, 2010

2009
Resource-efficient acceleration of 2-dimensional Fast Fourier Transform computations on FPGAs.
Proceedings of the Third ACM/IEEE International Conference on Distributed Smart Cameras, 2009

2008
Systematic generation of FPGA-based FFT implementations.
Proceedings of the IEEE International Conference on Acoustics, 2008


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