T. Hashimoto

According to our database, T. Hashimoto authored at least 3 papers between 2000 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Crossed Bit Line (CBL) Architecture in 3D Flash Memory CMOS Directly Bonded to Array (CBA) Structure.

Hiroshi Maejima, Katsuaki Isobe, N. Okada, Masaki Unno, T. Hashimoto, Tetsuaki Utsumi, T. Hisada, K. Maruyama, Toshiyuki Kouchi, T. Kotani, Hitoshi Shiga, O. Kwon, A. Ganguly, Y. Wu, Hiroki Yabe, I. Lu, F. Toyama, Naohito Morozumi, Masahito Takehara, Takuya Ariki, I. Yoon

Proceedings of the IEEE International Memory Workshop, 2025

2008

A single-chip 8-band CMOS transceiver for W-CDMA(HSPA) / GSM(GPRS) / EDGE with digital interface.

Hiroshi Yoshida, Takehiko Toyoda, T. Yasuda, Yosuke Ogasawara, M. Ishii, T. Murasaki, Gaku Takemura, Masaomi Iwanaga, T. Takida, Yuta Araki, T. Hashimoto, K. Sami, Teruo Imayama, H. Shimizu, Hideyuki Kokatsu, Y. Tsuda, I. Tamura, H. Masuoka, Masahiro Hosoya, R. Ito, Hidenori Okuni, T. Kato, K. Sato, K. Nonin, K. Osawa, R. Fujimoto, S. Kawaguchi, Hiroshi Tsurumi, Nobuyuki Itoh

Proceedings of the ESSCIRC 2008, 2008

2000

A fabrication method for high performance embedded DRAM of 0.18 μm generation and beyond.

T. Yoshida, H. Takato, T. Sakurai, K. Kokubun, K. Hiyama, A. Nomachi, Y. Takasu, M. Kishida, H. Ohtsuka, H. Naruse, Y. Morimasa, N. Yanagiya, T. Hashimoto, T. Noguchi, T. Miyamae, N. Iwabuchi, M. Tanaka, J. Kumagai, H. Ishiuchi

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000