Ta-Ching Yeh

According to our database, Ta-Ching Yeh authored at least 3 papers between 2008 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub- $\mu$ A Sensing Resolution, and 17.5-nS Read Access Time.

Yi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Ku-Feng Lin, Ta-Ching Yeh, Hung-Chang Yu, Harry Chuang, Yu-Der Chih, Tsung-Yung Jonathan Chang

IEEE J. Solid State Circuits, 2019

2018

Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time.

Yi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Ku-Feng Lin, Ta-Ching Yeh, Hung-Chang Yu, Harry Chuang, Yu-Der Chih, Tsung-Yung Jonathan Chang

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2008

Large-scale atomistic approach to random-dopant-induced characteristic variability in nanoscale CMOS digital and high-frequency integrated circuits.

Yiming Li, Chih-Hong Hwang, Ta-Ching Yeh, Tien-Yeh Li

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008