Harry Chuang
According to our database1,
Harry Chuang
authored at least 8 papers
between 2018 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 10<sup>12</sup> Write Endurance and Integrated Margin-Expansion Schemes.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
15.7 A 32Mb RRAM in a 12nm FinFet Technology with a 0.0249μm<sup>2</sup> Bit-Cell, a 3.2GB/S Read Throughput, a 10KCycle Write Endurance and a 10-Year Retention at 105°C.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2020
A 22nm 96KX144 RRAM Macro with a Self-Tracking Reference and a Low Ripple Charge Pump to Achieve a Configurable Read Window and a Wide Operating Voltage Range.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub- $\mu$ A Sensing Resolution, and 17.5-nS Read Access Time.
IEEE J. Solid State Circuits, 2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2018
Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018