Hon-Jarn Lin
According to our database1,
Hon-Jarn Lin
authored at least 7 papers
between 2013 and 2023.
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Collaborative distances:
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Bibliography
2023
A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2020
13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub- $\mu$ A Sensing Resolution, and 17.5-nS Read Access Time.
IEEE J. Solid State Circuits, 2019
2018
Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
2017
A 1.4Mb 40-nm embedded ReRAM macro with 0.07um<sup>2</sup> bit cell, 2.7mA/100MHz low-power read and hybrid write verify for high endurance application.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2014
Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
2013
A Two-Write and Two-Read Multi-Port SRAM with Shared Write Bit-Line Scheme and Selective Read Path for Low Power Operation.
J. Low Power Electron., 2013