Taeho Seong

According to our database, Taeho Seong authored at least 20 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation.

Juyeop Kim, Yongwoo Jo, Hangi Park, Taeho Seong, Younghyun Lim, Jaehyouk Choi

IEEE J. Solid State Circuits, February, 2024

2022

A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector.

Hangi Park, Chanwoong Hwang, Taeho Seong, Jaehyouk Choi

IEEE J. Solid State Circuits, 2022

A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM.

Chanwoong Hwang, Hangi Park, Yongsun Lee, Taeho Seong, Jaehyouk Choi

IEEE J. Solid State Circuits, 2022

A 188fsrms-Jitter and -243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector.

Chanwoong Hwang, Hangi Park, Taeho Seong, Jaehyouk Choi

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021

A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator.

Seyeon Yoo, Seojin Choi, Yongsun Lee, Taeho Seong, Younghyun Lim, Jaehyouk Choi

IEEE J. Solid State Circuits, 2021

A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping Δ ΣM.

Hangi Park, Chanwoong Hwang, Taeho Seong, Yongsun Lee, Jaehyouk Choi

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique.

Juyeop Kim, Yongwoo Jo, Younghyun Lim, Taeho Seong, Hangi Park, Seyeon Yoo, Yongsun Lee, Seojin Choi, Jaehyouk Choi

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020

17.3 A -58dBc-Worst-Fractional-Spur and -234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word.

Taeho Seong, Yongsun Lee, Chanwoong Hwang, Jeonghyun Lee, Hangi Park, Kyuho Jason Lee, Jaehyouk Choi

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

17.1 A -240dB-FoMjitter and -115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction.

Yongsun Lee, Taeho Seong, Jeonghyun Lee, Chanwoong Hwang, Hangi Park, Jaehyouk Choi

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

A 320-fs RMS Jitter and - 75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC.

Taeho Seong, Yongsun Lee, Seyeon Yoo, Jaehyouk Choi

IEEE J. Solid State Circuits, 2019

An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators.

Juyeop Kim, Younghyun Lim, Heein Yoon, Yongsun Lee, Hangi Park, Yoonseo Cho, Taeho Seong, Jaehyouk Choi

IEEE J. Solid State Circuits, 2019

A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator.

Seyeon Yoo, Seojin Choi, Yongsun Lee, Taeho Seong, Younghyun Lim, Jaehyouk Choi

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 76fsrms Jitter and -40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization.

Juyeop Kim, Heein Yoon, Younghyun Lim, Yongsun Lee, Yoonseo Cho, Taeho Seong, Jaehyouk Choi

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique.

Yongsun Lee, Taeho Seong, Seyeon Yoo, Jaehyouk Choi

IEEE J. Solid State Circuits, 2018

A -242dB FOM and -75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC.

Taeho Seong, Yongsun Lee, Seyeon Yoo, Jaehyouk Choi

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A switched-loop-filter PLL with fast phase-error correction technique.

Yongsun Lee, Taeho Seong, Seyeon Yoo, Jaehyouk Choi

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2016

A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-Time PVT Calibrator With Replica-Delay Cells.

Mina Kim, Seojin Choi, Taeho Seong, Jaehyouk Choi

IEEE J. Solid State Circuits, 2016

2015

Analysis and Design of a Core-Size-Scalable Low Phase Noise LC-VCO for Multi-Standard Cellular Transceivers.

Taeho Seong, Jae Joon Kim, Jaehyouk Choi

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for ΔΣ PLLs.

Yongsun Lee, Mina Kim, Taeho Seong, Jaehyouk Choi

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2014

Ultralow In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration.

Taeho Seong, Yongsun Lee, Jaehyouk Choi

IEEE Trans. Circuits Syst. II Express Briefs, 2014