Heein Yoon

According to our database1, Heein Yoon authored at least 12 papers between 2014 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
17.8 A 170MHz-Lock-In-Range and -253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration.
IEEE J. Solid State Circuits, 2019

An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators.
IEEE J. Solid State Circuits, 2019

A 76fsrms Jitter and -40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers.
IEEE J. Solid State Circuits, 2018

A -31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Injection-locked frequency multiplier with a continuous frequency-tracking loop for 5G transceivers.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
19.2 A PVT-robust -39dBc 1kHz-to-100MHz integrated-phase-noise 29GHz injection-locked frequency multiplier with a 600µW frequency-tracking loop using the averages of phase deviations for mm-band 5G transceivers.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

An ultra-low phase noise all-digital multi-frequency generator using injection-locked DCOs and time-interleaved calibration.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
A 0.56-2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2G-4G Multistandard Cellular Transceivers.
IEEE J. Solid State Circuits, 2016

A PVT-robust -59-dBc reference spur and 450-fsRMS jitter injection-locked clock multiplier using a voltage-domain period-calibrating loop.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2014
A Wideband Dual-Mode LC-VCO With a Switchable Gate-Biased Active Core.
IEEE Trans. Circuits Syst. II Express Briefs, 2014


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