Jeonghyun Lee
Orcid: 0000-0003-4487-364X
According to our database1,
Jeonghyun Lee
authored at least 34 papers
between 2006 and 2024.
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Bibliography
2024
Taking a stance in the process of learning: Developing perspectival understandings through knowledge co-construction during synchronous computer-mediated classroom discussion.
Int. J. Comput. Support. Collab. Learn., March, 2024
2023
Cognotyping by What-Where-When Retrieval Reveals the Potential Role of Temporal Memory and Its Neural Correlates in Understanding Individual Differences across Aging and Alzheimer Disease.
J. Cogn. Neurosci., November, 2023
A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68.
IEEE J. Solid State Circuits, 2023
Learning Vehicle Dynamics from Cropped Image Patches for Robot Navigation in Unpaved Outdoor Terrains.
CoRR, 2023
CoRR, 2023
Designing a Communication Bridge between Communities: Participatory Design for a Question-Answering AI Agent.
CoRR, 2023
A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102 - Multiplication Factor Using a Power-Gating Technique.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Managing the Chaos: Approaches to Navigating Discussion Forums for Instructional Staff.
Proceedings of the Tenth ACM Conference on Learning @ Scale, 2023
A 0.009mm2, 6.5mW, 6.2b-ENOB 2.5GS/s Flash-and-VCO-Based Subranging ADC Using a Resistor-Ladder-Based Residue Shifter.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
CoRR, 2022
Influential Text-Based Features in Predicting Admission Status of Online Degree Applicants.
Proceedings of the L@S'22: Ninth ACM Conference on Learning @ Scale, New York City, NY, USA, June 1, 2022
A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked Clock Multiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Model Stealing Defense against Exploiting Information Leak through the Interpretation of Deep Neural Nets.
Proceedings of the Thirty-First International Joint Conference on Artificial Intelligence, 2022
2021
Proceedings of the 21th International Conference on New Interfaces for Musical Expression, 2021
Comparative Analysis of the Feature Extraction Approaches for Predicting Learners Progress in Online Courses: MicroMasters Credential versus Traditional MOOCs.
Proceedings of the L@S'21: Eighth ACM Conference on Learning @ Scale, 2021
How Online Learners Build Cognitive Presence: Implications from a Machine Learning Approach.
Proceedings of the L@S'21: Eighth ACM Conference on Learning @ Scale, 2021
A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency.
Proceedings of the 47th ESSCIRC 2021, 2021
2020
Predicting Applicant Admission Status for Georgia Tech's Online Master's in Analytics Program.
Proceedings of the L@S'20: Seventh ACM Conference on Learning @ Scale, 2020
17.3 A -58dBc-Worst-Fractional-Spur and -234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
17.1 A -240dB-FoMjitter and -115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114.
IEEE J. Solid State Circuits, 2019
CoRR, 2019
A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2018
An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique.
IEEE J. Solid State Circuits, 2018
153 FSRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHZ Ring-LC-Hybrid Injection-Locked Clock Multiplier.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 320µV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
An external-capacitor-less high-PSR low-dropout regulator using an adaptive supply-ripple cancellation technique to the body-gate.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
An External Capacitor-Less Ultralow-Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power-Supply Rejection Over a Wide Range of Load Current.
IEEE Trans. Very Large Scale Integr. Syst., 2017
An extemal-capacitor-less low-dropout regulator with less than -36dB PSRR at all frequencies from 10kHz to 1GHz using an adaptive supply-ripple cancellation technique to the body-gate.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2006
Proceedings of the Next Generation Information Technologies and Systems, 2006
Proceedings of the Computational Science and Its Applications, 2006
OSGi based Service Mobility Management for Pervasive Computing Environments.
Proceedings of the IASTED International Conference on Internet and Multimedia Systems and Applications, 2006