Yongsun Lee
Orcid: 0000-0003-0654-9363
According to our database1,
Yongsun Lee
authored at least 27 papers
between 2014 and 2022.
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Bibliography
2022
A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM.
IEEE J. Solid State Circuits, 2022
A Functional Verification Study of Quantum Key Distribute Networks and Services with a Trusted Node applied in KOREN.
Proceedings of the 13th International Conference on Information and Communication Technology Convergence, 2022
2021
A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator.
IEEE J. Solid State Circuits, 2021
A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping Δ ΣM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
17.3 A -58dBc-Worst-Fractional-Spur and -234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
17.1 A -240dB-FoMjitter and -115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A 320-fs RMS Jitter and - 75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC.
IEEE J. Solid State Circuits, 2019
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators.
IEEE J. Solid State Circuits, 2019
An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114.
IEEE J. Solid State Circuits, 2019
A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 76fsrms Jitter and -40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers.
IEEE J. Solid State Circuits, 2018
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique.
IEEE J. Solid State Circuits, 2018
153 FSRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHZ Ring-LC-Hybrid Injection-Locked Clock Multiplier.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A -31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A -242dB FOM and -75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 320µV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
Injection-locked frequency multiplier with a continuous frequency-tracking loop for 5G transceivers.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
An External Capacitor-Less Ultralow-Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power-Supply Rejection Over a Wide Range of Load Current.
IEEE Trans. Very Large Scale Integr. Syst., 2017
19.2 A PVT-robust -39dBc 1kHz-to-100MHz integrated-phase-noise 29GHz injection-locked frequency multiplier with a 600µW frequency-tracking loop using the averages of phase deviations for mm-band 5G transceivers.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
A 0.56-2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2G-4G Multistandard Cellular Transceivers.
IEEE J. Solid State Circuits, 2016
A PVT-robust -59-dBc reference spur and 450-fsRMS jitter injection-locked clock multiplier using a voltage-domain period-calibrating loop.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
2015
A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for ΔΣ PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Ultralow In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, 2014