Taeho Shin

Orcid: 0009-0003-8244-4835

According to our database¹, Taeho Shin authored at least 8 papers between 2021 and 2025.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

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2025

100-112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3 + 1 Hybrid FFE Taps in 40-nm Technology.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, February, 2025

Process-Portable Layout Generation of High-Speed Digital Circuit Using Standard Cells in FinFET.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on Synthesis, 2025

A 56-Gb/s 0.39-pJ/bit PAM-4 Transmitter Frontend with Shunt-Ffe Tail-Less Driver and External Bias-Tees.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024

A 100-Gb/s PAM-8 Transmitter With 3-Tap FFE and High-Swing Hybrid Driver in 40-nm CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, June, 2024

2023

LAYGO2: A Custom Layout Generation Engine Based on Dynamic Templates and Grids for Advanced CMOS Technologies.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

A 100Gb/s 1.6Vppd PAM-8 Transmitter with High-Swing 3+1 Hybrid FFE Taps in 40nm.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022

A Custom IC Layout Generation Engine Based on Dynamic Templates and Grids.

[BibT_eX]

[DOI]

CoRR, 2022

2021

A SCAN Chain Generator for Verification of Full-Custom Integrated Circuits.

[BibT_eX]

[DOI]

Taeho Shin

Jaeduk Han

Proceedings of the 18th International SoC Design Conference, 2021

Taeho Shin

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