Tai-Hsuan Wu

VLSI Design, 2013

2011

GRIP: Global Routing via Integer Programming.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Power-driven global routing for multi-supply voltage domains.

[BibT_eX]

[DOI]

Jeff T. Linderoth

Proceedings of the Design, Automation and Test in Europe, 2011

2010

A pareto-algebraic framework for signal power optimization in global routing.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

A parallel integer programming approach to global routing.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2009

Adjustment-Based Modeling for Timing Analysis Under Variability.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

PaRS: Parallel and Near-Optimal Grid-Based Cell Sizing for Library-Based Design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

GRIP: scalable 3D global routing using integer programming.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

A Parallel and Randomized Algorithm for Large-Scale Discrete Dual-Vt Assignment and Continuous Gate Sizing.

[BibT_eX]

[DOI]

Lin Xie

J. Low Power Electron., 2008

SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement.

[BibT_eX]

[DOI]

Anuj Kumar

Proceedings of the 26th International Conference on Computer Design, 2008

Adjustment-based modeling for statistical static timing analysis with high dimension of variability.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

PaRS: fast and near-optimal grid-based cell sizing for library-based design.

[BibT_eX]

[DOI]