Azadeh Davoodi

ACM Trans. Reconfigurable Technol. Syst., March, 2023

ObfusX: Routing obfuscation with explanatory analysis of a machine learning attack.

[BibT_eX]

[DOI]

Integr., March, 2023

Block Pruning for Enhanced Efficiency in Convolutional Neural Networks.

[BibT_eX]

[DOI]

Cheng-En Wu

CoRR, 2023

Neural Network Partitioning for Fast Distributed Inference.

[BibT_eX]

[DOI]

Robert Viramontes

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

2022

CAP'NN: A Class-aware Framework for Personalized Neural Network Inference.

[BibT_eX]

[DOI]

Joshua San Miguel

ACM Trans. Embed. Comput. Syst., September, 2022

$\text{Edge}^{n}$ AI: Distributed Inference with Local Edge Devices and Minimal Latency.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

AirNN: A Featherweight Framework for Dynamic Input-Dependent Approximation of CNNs.

[BibT_eX]

[DOI]

Joshua San Miguel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

A Mixture of Experts Approach for Low-Cost DNN Customization.

[BibT_eX]

[DOI]

IEEE Des. Test, 2021

Lorax: Machine Learning-Based Oracle Reconstruction With Minimal I/O Patterns.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Sampling-Based Approximate Logic Synthesis: An Explainable Machine Learning Approach.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Explainable DRC Hotspot Prediction with Random Forest and SHAP Tree Explainer.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

CAP'NN: Class-Aware Personalized Neural Network Inference.

[BibT_eX]

[DOI]

Joshua San Miguel

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

CHaPR: Efficient Inference of CNNs via Channel Pruning.

[BibT_eX]

[DOI]

Proceedings of the 2020 International Conference on Omni-layer Intelligent Systems, 2020

2019

Analysis of Security of Split Manufacturing Using Machine Learning.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Power-efficient ReRAM-aware CNN model generation.

[BibT_eX]

[DOI]

Integr., 2019

Efficient Inference of CNNs via Channel Pruning.

[BibT_eX]

[DOI]

CoRR, 2019

Dynamic Reconfiguration of CNNs for Input-Dependent Approximation.

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

2018

Exploring Energy and Accuracy Tradeoff in Structure Simplification of Trained Deep Neural Networks.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Design Rule Violation Hotspot Prediction Based on Neural Network Ensembles.

[BibT_eX]

[DOI]

CoRR, 2018

A Mixture of Expert Approach for Low-Cost Customization of Deep Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2018

A Comparative Study of Local Net Modeling Using Machine Learning.

[BibT_eX]

[DOI]

Jackson Melchert

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Analysis of security of split manufacturing using machine learning.

[BibT_eX]

[DOI]

Jonathon Crandall Magaña

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Are Proximity Attacks a Threat to the Security of Split Manufacturing of Integrated Circuits?

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Dynamic Planning of Local Congestion From Varying-Size Vias for Global Routing Layer Assignment.

[BibT_eX]

[DOI]

Edward Tashjian

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Improving Detailed Routability and Pin Access with 3D Monolithic Standard Cells.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Technology mapping with all spin logic.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

TraPL: Track Planning of Local Congestion for Global Routing.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Flexible interconnect in 2.5D ICs to minimize the interposer's metal layers.

[BibT_eX]

[DOI]

Daniel P. Seemuth

Katherine Morrow

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Preface to Special Section on New Physical Design Techniques for the Next Generation of Integration Technology.

[BibT_eX]

[DOI]

Evangeline F. Y. Young

ACM Trans. Design Autom. Electr. Syst., 2016

Are proximity attacks a threat to the security of split manufacturing of integrated circuits?

[BibT_eX]

[DOI]

Jonathon Magaña

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A procedure for improving the distribution of congestion in global routing.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes.

[BibT_eX]

[DOI]

Jiang Hu

Muhammet Mustafa Ozdal

Cliff C. N. Sze

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Automatic die placement and flexible I/O assignment in 2.5D IC design.

[BibT_eX]

[DOI]

Daniel P. Seemuth

Katherine Morrow

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Online and Operand-Aware Detection of Failures Utilizing False Alarm Vectors.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

On using control signals for word-level identification in a gate-level netlist.

[BibT_eX]

[DOI]

Edward Tashjian

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

A Hybrid Approach for Fast and Accurate Trace Signal Selection for Post-Silicon Debug.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Multi-mode trace signal selection for post-silicon debug.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Power-Driven Global Routing for Multisupply Voltage Domains.

[BibT_eX]

[DOI]

VLSI Design, 2013

Collaborative Multiobjective Global Routing.

[BibT_eX]

[DOI]

Twan Basten

IEEE Trans. Very Large Scale Integr. Syst., 2013

A fast and scalable multidimensional multiple-choice knapsack heuristic.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2013

A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection.

[BibT_eX]

[DOI]

Mohammad Tehranipoor

IEEE Des. Test, 2013

Planning for local net congestion in global routing.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2013

2012

Post-Silicon Failing-Path Isolation Incorporating the Effects of Process Variations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Confidentiality preserving integer programming for global routing.

[BibT_eX]

[DOI]

Parmeswaran Ramanathan

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Bound-Based Statistically-Critical Path Extraction Under Process Variations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

GRIP: Global Routing via Integer Programming.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Congestion analysis for global routing via integer programming.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Power-driven global routing for multi-supply voltage domains.

[BibT_eX]

[DOI]

Jeff T. Linderoth

Proceedings of the Design, Automation and Test in Europe, 2011

2010

A pareto-algebraic framework for signal power optimization in global routing.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Trace signal selection to enhance timing and logic visibility in post-silicon validation.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations.

[BibT_eX]

[DOI]

Kewal K. Saluja

Proceedings of the 47th Design Automation Conference, 2010

Representative path selection for post-silicon timing prediction under variability.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

A parallel integer programming approach to global routing.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Runtime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processors.

[BibT_eX]

[DOI]

Dongkeun Oh

Nam Sung Kim

Charlie Chung-Ping Chen

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Adjustment-Based Modeling for Timing Analysis Under Variability.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

PaRS: Parallel and Near-Optimal Grid-Based Cell Sizing for Library-Based Design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

False Path Aware Timing Yield Estimation under Variability.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Statistical static timing analysis considering leakage variability in power gated designs.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

GRIP: scalable 3D global routing using integer programming.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

Bound-based identification of timing-violating paths under variability.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Variability Driven Gate Sizing for Binning Yield Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Robust Estimation of Timing Yield With Partial Statistical Information on Process Variations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A Parallel and Randomized Algorithm for Large-Scale Discrete Dual-Vt Assignment and Continuous Gate Sizing.

[BibT_eX]

[DOI]

J. Low Power Electron., 2008

Fast and accurate statistical static timing analysis with skewed process parameter variation.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2008

A Dual-Vt low leakage SRAM array robust to process variations.

[BibT_eX]

[DOI]

Jungseob Lee

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement.

[BibT_eX]

[DOI]

Anuj Kumar

Proceedings of the 26th International Conference on Computer Design, 2008

Adjustment-based modeling for statistical static timing analysis with high dimension of variability.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

PaRS: fast and near-optimal grid-based cell sizing for library-based design.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007

Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Comparison of Dual-Vt Configurations of SRAM Cell Considering Process-Induced Vt Variations.

[BibT_eX]

[DOI]

Jungseob Lee

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Statistical timing analysis using Kernel smoothing.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Computer Design, 2007

2006

Effective techniques for the generalized low-power binding problem.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2006

A statistical methodology for wire-length prediction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Probabilistic Evaluation of Solutions in Variability-Driven Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

FPGA Dynamic Power Minimization through Placement and Routing Constraints.

[BibT_eX]

[DOI]

EURASIP J. Embed. Syst., 2006

Probabilistic evaluation of solutions in variability-driven optimization.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Physical Design, 2006

2005

Simultaneous V<sub>t</sub> selection and assignment for leakage optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

Power-driven simultaneous resource binding and floorplanning: a probabilistic approach.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

Voltage scheduling under unpredictabilities: a risk management paradigm.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2005

Probabilistic dual-Vth leakage optimization under variability.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Variability-Driven Buffer Insertion Considering Correlations.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Wake-up protocols for controlling current surges in MTCMOS-based technology.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Simultaneous floorplanning and resource binding: a probabilistic approach.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Empirical models for net-length probability distribution and applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Wire-length prediction using statistical techniques.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Efficient statistical timing analysis through error budgeting.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Variability inspired implementation selection problem.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

High level techniques for power-grid noise immunity.

[BibT_eX]

[DOI]

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003

Effective graph theoretic techniques for the generalized low power binding problem.

[BibT_eX]

[DOI]