Tai-Ying Jiang

According to our database1, Tai-Ying Jiang authored at least 6 papers between 2002 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2009
Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

2007
Observability Analysis on HDL Descriptions for Effective Functional Validation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2005
Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An observability measure to enhance statement coverage metric for proper evaluation of verification completeness.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
An efficient logic extraction algorithm using partitioning and circuit encoding.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2002
Effective Error Diagnosis for RTL Designs in HDLs.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002


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