Taizhi Liu

According to our database1, Taizhi Liu authored at least 21 papers between 2014 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
SRAM Stability Analysis and Performance-Reliability Tradeoff for Different Cache Configurations.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Inverse Design of FinFET SRAM Cells.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019
Impact of Front-End Wearout Mechanisms on the Performance of a Ring Oscillator-Based Thermal Sensor.
Proceedings of the IEEE 8th International Workshop on Advances in Sensors and Interfaces, 2019

2018
A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator for Both Traditional CMOS and FinFET Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Comprehensive Reliability-Aware Statistical Timing Analysis Using a Unified Gate-Delay Model for Microprocessors.
IEEE Trans. Emerg. Top. Comput., 2018

Circuit-level reliability simulator for front-end-of-line and middle-of-line time-dependent dielectric breakdown in FinFET technology.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Estimation of the Optimal Accelerated Test Region for FinFET SRAMs Degraded by Front-End and Back-End Wearout Mechanisms.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

Optimal Accelerated Test Regions for Time- Dependent Dielectric Breakdown Lifetime Parameters Estimation in FinFET Technology.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017
Negative Bias Temperature Instability and Gate Oxide Breakdown Modeling in Circuits With Die-to-Die Calibration Through Power Supply and Ground Signal Measurements.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Analysis of time-dependent dielectric breakdown induced aging of SRAM cache with different configurations.
Microelectron. Reliab., 2017

Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits.
Microelectron. Reliab., 2017

On-line monitoring of system health using on-chip SRAMs as a wearout sensor.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

2016
System-Level Modeling of Microprocessor Reliability Degradation Due to Bias Temperature Instability and Hot Carrier Injection.
IEEE Trans. Very Large Scale Integr. Syst., 2016

SRAM stability analysis for different cache configurations due to Bias Temperature Instability and Hot Carrier Injection.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015
Comprehensive reliability and aging analysis on SRAMs within microprocessor systems.
Microelectron. Reliab., 2015

System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown.
Microelectron. Reliab., 2015

The die-to-die calibrated combined model of negative bias temperature instability and gate oxide breakdown from device to system.
Microelectron. Reliab., 2015

Processor-level reliability simulator for time-dependent gate dielectric breakdown.
Microprocess. Microsystems, 2015

Estimation of remaining life using embedded SRAM for wearout parameter extraction.
Proceedings of the 6th International Workshop on Advances in Sensors and Interfaces, 2015

Accurate standard cell characterization and statistical timing analysis using multivariate adaptive regression splines.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2014
Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014


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