Linda S. Milor
Orcid: 0000-0002-8244-4793Affiliations:
- Georgia Institute of Technology, Atlanta, USA
According to our database1,
Linda S. Milor
authored at least 82 papers
between 1986 and 2022.
Collaborative distances:
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Bibliography
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
2021
A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2021
2020
SRAM Stability Analysis and Performance-Reliability Tradeoff for Different Cache Configurations.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Optimal Accelerated Test Framework for Time-Dependent Dielectric Breakdown Lifetime Parameter Estimation.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
2019
Optimization of Experimental Designs for System- Level Accelerated Life Test in a Memory System Degraded by Time-Dependent Dielectric Breakdown.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Impact of Front-End Wearout Mechanisms on the Performance of a Ring Oscillator-Based Thermal Sensor.
Proceedings of the IEEE 8th International Workshop on Advances in Sensors and Interfaces, 2019
Proceedings of the IEEE International Reliability Physics Symposium, 2019
Identification of Failure Modes for Circuit Samples with Confounded Causes of Failure.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019
2018
A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator for Both Traditional CMOS and FinFET Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Comprehensive Reliability-Aware Statistical Timing Analysis Using a Unified Gate-Delay Model for Microprocessors.
IEEE Trans. Emerg. Top. Comput., 2018
Circuit-level reliability simulator for front-end-of-line and middle-of-line time-dependent dielectric breakdown in FinFET technology.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Estimation of the Optimal Accelerated Test Region for FinFET SRAMs Degraded by Front-End and Back-End Wearout Mechanisms.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
Optimal Accelerated Test Regions for Time- Dependent Dielectric Breakdown Lifetime Parameters Estimation in FinFET Technology.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Negative Bias Temperature Instability and Gate Oxide Breakdown Modeling in Circuits With Die-to-Die Calibration Through Power Supply and Ground Signal Measurements.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Analysis of time-dependent dielectric breakdown induced aging of SRAM cache with different configurations.
Microelectron. Reliab., 2017
Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits.
Microelectron. Reliab., 2017
Analysis of errors in estimating wearout characteristics of time-dependent dielectric breakdown using system-level accelerated life test.
Microelectron. Reliab., 2017
A methodology for estimating memory lifetime using a system-level accelerated life test and error-correcting codes.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
Adaptive supply voltage and duty cycle controller for yield-power optimization of ICs.
Proceedings of the 7th IEEE International Workshop on Advances in Sensors and Interfaces, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
2016
Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array.
IEEE Trans. Very Large Scale Integr. Syst., 2016
System-Level Modeling of Microprocessor Reliability Degradation Due to Bias Temperature Instability and Hot Carrier Injection.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
SRAM stability analysis for different cache configurations due to Bias Temperature Instability and Hot Carrier Injection.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
2015
Microprocessor Aging Analysis and Reliability Modeling Due to Back-End Wearout Mechanisms.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Microelectron. Reliab., 2015
System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown.
Microelectron. Reliab., 2015
Built-in self-test for bias temperature instability, hot-carrier injection, and gate oxide breakdown in embedded DRAMs.
Microelectron. Reliab., 2015
Microelectron. Reliab., 2015
The die-to-die calibrated combined model of negative bias temperature instability and gate oxide breakdown from device to system.
Microelectron. Reliab., 2015
Microprocess. Microsystems, 2015
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
MBIST and statistical hypothesis test for time dependent dielectric breakdowns due to GOBD vs. BTDDB in an SRAM array.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Proceedings of the 6th International Workshop on Advances in Sensors and Interfaces, 2015
Accurate standard cell characterization and statistical timing analysis using multivariate adaptive regression splines.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Built-in self test methodology for diagnosis of backend wearout mechanisms in SRAM cells.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
2013
Impact of NBTI/PBTIon SRAMs within microprocessor systems: Modeling, simulation, and analysis.
Microelectron. Reliab., 2013
Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013
System-level modeling and microprocessor reliability analysis for backend wearout mechanisms.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
Microelectron. Reliab., 2012
Microelectron. Reliab., 2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
2011
Microelectron. Reliab., 2011
2010
Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown.
Microelectron. Reliab., 2010
Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
A methodology to extract failure rates for low-k dielectric breakdown with multiple geometries and in the presence of die-to-die linewidth variation.
Microelectron. Reliab., 2009
IEEE Des. Test Comput., 2009
Proceedings of the 27th International Conference on Computer Design, 2009
Proceedings of the CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
2007
Microelectron. Reliab., 2007
Microelectron. Reliab., 2007
2006
Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
2005
Study of Area Scaling Effect on Integrated Circuit Reliability Based on Yield Models.
Microelectron. Reliab., 2005
2004
Analysis of the layout impact on electric fields in interconnect structures using finite element method.
Microelectron. Reliab., 2004
2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
2002
Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
2000
Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
1996
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996
Proceedings of the 33st Conference on Design Automation, 1996
1994
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
1990
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990
1989
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989
1986
An Efficient Algorithm to Determine the Image of a Parallelepiped Under a Linear Transformation.
Proceedings of the Second Annual ACM SIGACT/SIGGRAPH Symposium on Computational Geometry, 1986