Linda S. Milor

According to our database1, Linda S. Milor authored at least 75 papers between 1986 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Optimization of Experimental Designs for System- Level Accelerated Life Test in a Memory System Degraded by Time-Dependent Dielectric Breakdown.
IEEE Trans. VLSI Syst., 2019

Impact of Front-End Wearout Mechanisms on the Performance of a Ring Oscillator-Based Thermal Sensor.
Proceedings of the IEEE 8th International Workshop on Advances in Sensors and Interfaces, 2019

Machine Learning for Detection of Competing Wearout Mechanisms.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

2018
A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator for Both Traditional CMOS and FinFET Technology.
IEEE Trans. VLSI Syst., 2018

Comprehensive Reliability-Aware Statistical Timing Analysis Using a Unified Gate-Delay Model for Microprocessors.
IEEE Trans. Emerging Topics Comput., 2018

Circuit-level reliability simulator for front-end-of-line and middle-of-line time-dependent dielectric breakdown in FinFET technology.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Estimation of the Optimal Accelerated Test Region for FinFET SRAMs Degraded by Front-End and Back-End Wearout Mechanisms.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

Optimal Accelerated Test Regions for Time- Dependent Dielectric Breakdown Lifetime Parameters Estimation in FinFET Technology.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017
An ECC-Assisted Postpackage Repair Methodology in Main Memory Systems.
IEEE Trans. VLSI Syst., 2017

Negative Bias Temperature Instability and Gate Oxide Breakdown Modeling in Circuits With Die-to-Die Calibration Through Power Supply and Ground Signal Measurements.
IEEE Trans. VLSI Syst., 2017

Analysis of time-dependent dielectric breakdown induced aging of SRAM cache with different configurations.
Microelectronics Reliability, 2017

Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits.
Microelectronics Reliability, 2017

Analysis of errors in estimating wearout characteristics of time-dependent dielectric breakdown using system-level accelerated life test.
Microelectronics Reliability, 2017

A methodology for estimating memory lifetime using a system-level accelerated life test and error-correcting codes.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Adaptive supply voltage and duty cycle controller for yield-power optimization of ICs.
Proceedings of the 7th IEEE International Workshop on Advances in Sensors and Interfaces, 2017

On-line monitoring of system health using on-chip SRAMs as a wearout sensor.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

2016
Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array.
IEEE Trans. VLSI Syst., 2016

System-Level Modeling of Microprocessor Reliability Degradation Due to Bias Temperature Instability and Hot Carrier Injection.
IEEE Trans. VLSI Syst., 2016

Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs.
IEEE Trans. VLSI Syst., 2016

ECC-ASPIRIN: An ECC-assisted post-package repair scheme for aging errors in DRAMs.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

SRAM stability analysis for different cache configurations due to Bias Temperature Instability and Hot Carrier Injection.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015
Microprocessor Aging Analysis and Reliability Modeling Due to Back-End Wearout Mechanisms.
IEEE Trans. VLSI Syst., 2015

Comprehensive reliability and aging analysis on SRAMs within microprocessor systems.
Microelectronics Reliability, 2015

System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown.
Microelectronics Reliability, 2015

Built-in self-test for bias temperature instability, hot-carrier injection, and gate oxide breakdown in embedded DRAMs.
Microelectronics Reliability, 2015

AVERT: An elaborate model for simulating variable retention time in DRAMs.
Microelectronics Reliability, 2015

The die-to-die calibrated combined model of negative bias temperature instability and gate oxide breakdown from device to system.
Microelectronics Reliability, 2015

Processor-level reliability simulator for time-dependent gate dielectric breakdown.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Panel: Analog/RF BIST: Are we there yet?
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

MBIST and statistical hypothesis test for time dependent dielectric breakdowns due to GOBD vs. BTDDB in an SRAM array.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Estimation of remaining life using embedded SRAM for wearout parameter extraction.
Proceedings of the 6th International Workshop on Advances in Sensors and Interfaces, 2015

Accurate standard cell characterization and statistical timing analysis using multivariate adaptive regression splines.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2014
Backend Dielectric Reliability Full Chip Simulator.
IEEE Trans. VLSI Syst., 2014

Simulation of system backend dielectric reliability.
Microelectronics Journal, 2014

Built-in self test methodology for diagnosis of backend wearout mechanisms in SRAM cells.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

2013
Impact of NBTI/PBTIon SRAMs within microprocessor systems: Modeling, simulation, and analysis.
Microelectronics Reliability, 2013

A Delay Evaluation Circuit for Analog BIST Function.
IEICE Transactions, 2013

System-level modeling and reliability analysis of microprocessor systems.
Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013

System-level modeling and microprocessor reliability analysis for backend wearout mechanisms.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Analysis and On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells.
IEEE Trans. VLSI Syst., 2012

Statistical model of NBTI and reliability simulation for analogue circuits.
Microelectronics Reliability, 2012

Backend dielectric reliability simulator for microprocessor system.
Microelectronics Reliability, 2012

Wearout-aware compiler-directed register assignment for embedded systems.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

A comparative study of wearout mechanisms in state-of-art microprocessors.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Impact of NBTI on analog components.
Proceedings of the 17th IEEE European Test Symposium, 2012

2011
Impact of irregular geometries on low-k dielectric breakdown.
Microelectronics Reliability, 2011

2010
Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown.
Microelectronics Reliability, 2010

Via wearout detection with on-chip monitors.
Microelectronics Journal, 2010

Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Towards a chip level reliability simulator for copper/low-k backend processes.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
A DLL Design for Testing I/O Setup and Hold Times.
IEEE Trans. VLSI Syst., 2009

A methodology to extract failure rates for low-k dielectric breakdown with multiple geometries and in the presence of die-to-die linewidth variation.
Microelectronics Reliability, 2009

Modeling Low-k Dielectric Breakdown to Determine Lifetime Requirements.
IEEE Design & Test of Computers, 2009

Reliable cache design with detection of gate oxide breakdown using BIST.
Proceedings of the 27th International Conference on Computer Design, 2009

Fast Variation-Aware Statistical Dynamic Timing Analysis.
Proceedings of the CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31, 2009

Timing Analysis with Compact Variation-Aware Standard Cell Models.
Proceedings of the CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31, 2009

2008
A BIST Circuit for DLL Fault Detection.
IEEE Trans. VLSI Syst., 2008

Diagnosis of Optical Lithography Faults With Product Test Sets.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007
Backend dielectric breakdown dependence on linewidth and pattern density.
Microelectronics Reliability, 2007

Modeling of the breakdown mechanisms for porous copper/low-k process flows.
Microelectronics Reliability, 2007

2006
Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

2005
Study of Area Scaling Effect on Integrated Circuit Reliability Based on Yield Models.
Microelectronics Reliability, 2005

2004
Analysis of the layout impact on electric fields in interconnect structures using finite element method.
Microelectronics Reliability, 2004

2003
A BIST Solution for The Test of I/O Speed.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

2000
Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1996
Is High Frequency Analog DFT Possible?
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Computing Parametric Yield Adaptively Using Local Linear Models.
Proceedings of the 33st Conference on Design Automation, 1996

1994
Minimizing production test time to detect faults in analog circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

1990
Optimal Test Set Design for Analog Circuits.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Computing Parametric Yield Accurately and Efficiently.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989
Detection of catastrophic faults in analog integrated circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1989

1986
An Efficient Algorithm to Determine the Image of a Parallelepiped Under a Linear Transformation.
Proceedings of the Second Annual ACM SIGACT/SIGGRAPH Symposium on Computational Geometry, 1986


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