# Takakazu Kurokawa

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^{1}, Takakazu Kurokawa## Timeline

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## Bibliography

2015

Search Algorithm of Precise Integral Distinguisher of Byte-Based Block Cipher.

Proceedings of the Information Systems Security - 11th International Conference, 2015

Improved GPU Implementation of RainbowCrack.

Proceedings of the Third International Symposium on Computing and Networking, 2015

Computational Security Evaluation of Light-Weight Block Cipher Against Integral Attack by GPGPU.

Proceedings of the IEEE 2nd International Conference on Cyber Security and Cloud Computing, 2015

Integral Attack on Reduced-Round Rectangle.

Proceedings of the IEEE 2nd International Conference on Cyber Security and Cloud Computing, 2015

2014

Throughput and Power Efficiency Evaluation of Block Ciphers on Kepler and GCN GPUs Using Micro-Benchmark Analysis.

IEICE Transactions, 2014

Analysis of Side-Channel Attack Based on Information Theory.

IEICE Transactions, 2014

Analysis of Slow Read DoS attack.

Proceedings of the International Symposium on Information Theory and its Applications, 2014

Intrusion detection system using Discrete Fourier Transform.

Proceedings of the Seventh IEEE Symposium on Computational Intelligence for Security and Defense Applications, 2014

2013

HiCrypt: A Specialized Translator for Symmetric Block Cipher and GPGPU.

IEICE Transactions, 2013

Performance Prediction Model for Block Ciphers on GPU Architectures.

Proceedings of the Network and System Security - 7th International Conference, 2013

Information Theoretical Analysis of Side-Channel Attack.

Proceedings of the Information Systems Security - 9th International Conference, 2013

Throughput and Power Efficiency Evaluations of Block Ciphers on Kepler and GCN GPUs.

Proceedings of the First International Symposium on Computing and Networking, 2013

2012

High-Performance Symmetric Block Ciphers on Multicore CPU and GPUs.

IJNC, 2012

Acceleration of AES encryption on CUDA GPU.

IJNC, 2012

Power Efficiency Evaluation of Block Ciphers on GPU-Integrated Multicore Processor.

Proceedings of the Algorithms and Architectures for Parallel Processing, 2012

A Correlation Power Analysis Countermeasure for Enocoro-128 v2 Using Random Switching Logic.

Proceedings of the Third International Conference on Networking and Computing, 2012

HiCrypt: C to CUDA Translator for Symmetric Block Ciphers.

Proceedings of the Third International Conference on Networking and Computing, 2012

2011

High-Performance Symmetric Block Ciphers on CUDA.

Proceedings of the Second International Conference on Networking and Computing, 2011

2010

AES Encryption Implementation on CUDA GPU and Its Analysis.

Proceedings of the First International Conference on Networking and Computing, 2010

2006

A flexible multiport content-addressable memory.

Systems and Computers in Japan, 2006

Neural network approach to the optimal lut assignment in FPGA for parallel multipliers over GF(2n).

Proceedings of the Artificial Intelligence and Soft Computing, 2006

2005

Finite Field Parallel Multiplier for FPGA.

Proceedings of the 4th European Conference on Information Warfare and Security, 2005

2004

Air transportation planning using neural networks as an example of the transportation squadron in the Japan Air Self-Defense Force.

Systems and Computers in Japan, 2004

Javar-kai: Automatic parallelizing compiler.

Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2004

2003

SEBSW-2: SEcret-Key Block Cipher SWitcher.

Proceedings of the International Conference on VLSI, 2003

2001

Neural network approach to the ECM problem.

Systems and Computers in Japan, 2001

1993

Realization of a self-testing bus arbiter.

Systems and Computers in Japan, 1993

1992

A Proposal of Fault-Checking Fuzzy Control.

Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992

1988

3-D VLSI technology in Japan and an example: a syndrome decoder for double error correction.

Future Generation Comp. Syst., 1988

1985

Polynomial Transformer.

Proceedings of the 7th IEEE Symposium on Computer Arithmetic, 1985

1983

New Matrix Equation Solvers in GF(2) Employing Cramer with Chio Method.

Proceedings of the International Conference on Parallel Processing, 1983

Fast matrix solver in GF(2).

Proceedings of the 6th IEEE Symposium on Computer Arithmetic, 1983