Keisuke Iwai

According to our database1, Keisuke Iwai authored at least 35 papers between 1999 and 2022.

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Bibliography

2022
FPGA Implementation of Stream Cipher SOSEMANUK.
Proceedings of the 2022 Tenth International Symposium on Computing and Networking, CANDAR 2022, 2022

2021
Acceleration and higher precision by discrete wavelet transform for single image super-resolution using convolutional neural networks.
Proceedings of the Ninth International Symposium on Computing and Networking, 2021

2020
A Translator from FDL to SystemVerilog for FPGA Implementation of Fuzzy Inference.
Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

2019
Implementation of high speed hash function Keccak on GPU.
Int. J. Netw. Comput., 2019

2018
Learning Accelerator of Deep Neural Networks with Logarithmic Quantization.
Proceedings of the 7th International Congress on Advanced Applied Informatics, 2018

AQSS: Accelerator of Quantization Neural Networks with Stochastic Approach.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018

2017
Implementation of Bitsliced AES Encryption on CUDA-Enabled GPU.
Proceedings of the Network and System Security - 11th International Conference, 2017

Implementation of Hash Function Generator on Schematic to Program Translator(SPT).
Proceedings of the Fifth International Symposium on Computing and Networking, 2017

Implementation of High Speed Hash Function Keccak Using CUDA on GTX 1080.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017

2015
Search Algorithm of Precise Integral Distinguisher of Byte-Based Block Cipher.
Proceedings of the Information Systems Security - 11th International Conference, 2015

Improved GPU Implementation of RainbowCrack.
Proceedings of the Third International Symposium on Computing and Networking, 2015

Computational Security Evaluation of Light-Weight Block Cipher Against Integral Attack by GPGPU.
Proceedings of the IEEE 2nd International Conference on Cyber Security and Cloud Computing, 2015

Integral Attack on Reduced-Round Rectangle.
Proceedings of the IEEE 2nd International Conference on Cyber Security and Cloud Computing, 2015

2014
Throughput and Power Efficiency Evaluation of Block Ciphers on Kepler and GCN GPUs Using Micro-Benchmark Analysis.
IEICE Trans. Inf. Syst., 2014

Analysis of Side-Channel Attack Based on Information Theory.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Analysis of Slow Read DoS attack.
Proceedings of the International Symposium on Information Theory and its Applications, 2014

Intrusion detection system using Discrete Fourier Transform.
Proceedings of the Seventh IEEE Symposium on Computational Intelligence for Security and Defense Applications, 2014

2013
HiCrypt: A Specialized Translator for Symmetric Block Cipher and GPGPU.
IEICE Trans. Inf. Syst., 2013

Performance Prediction Model for Block Ciphers on GPU Architectures.
Proceedings of the Network and System Security - 7th International Conference, 2013

Information Theoretical Analysis of Side-Channel Attack.
Proceedings of the Information Systems Security - 9th International Conference, 2013

Throughput and Power Efficiency Evaluations of Block Ciphers on Kepler and GCN GPUs.
Proceedings of the First International Symposium on Computing and Networking, 2013

2012
High-Performance Symmetric Block Ciphers on Multicore CPU and GPUs.
Int. J. Netw. Comput., 2012

Acceleration of AES encryption on CUDA GPU.
Int. J. Netw. Comput., 2012

Power Efficiency Evaluation of Block Ciphers on GPU-Integrated Multicore Processor.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2012

A Correlation Power Analysis Countermeasure for Enocoro-128 v2 Using Random Switching Logic.
Proceedings of the Third International Conference on Networking and Computing, 2012

HiCrypt: C to CUDA Translator for Symmetric Block Ciphers.
Proceedings of the Third International Conference on Networking and Computing, 2012

2011
High-Performance Symmetric Block Ciphers on CUDA.
Proceedings of the Second International Conference on Networking and Computing, 2011

2010
AES Encryption Implementation on CUDA GPU and Its Analysis.
Proceedings of the First International Conference on Networking and Computing, 2010

2006
A flexible multiport content-addressable memory.
Syst. Comput. Jpn., 2006

2005
Finite Field Parallel Multiplier for FPGA.
Proceedings of the 4th European Conference on Information Warfare and Security, 2005

2004
Javar-kai: Automatic parallelizing compiler.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2004

2003
MAPLE chip: a processing element for a static scheduling centric multiprocessor.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2000
Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware.
Proceedings of the Field-Programmable Logic and Applications, 2000

1999
Implementation and Evaluation of the Compiler for WASMII, a Virtual Hardware System.
Proceedings of the 1999 International Conference on Parallel Processing Workshops, 1999

Floating Point Arithmetic Unit for the Custom Processor Maple.
Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999


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