Takanori Hayashida

According to our database, Takanori Hayashida authored at least 7 papers between 2011 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

Improving timing error tolerance without impact on chip area and power consumption.

Ken Yano, Takanori Hayashida, Toshinori Sato

Proceedings of the International Symposium on Quality Electronic Design, 2013

2012

A Selective Replacement Method for Timing-Error-Predicting flip-Flops.

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida

J. Circuits Syst. Comput., 2012

Analysis of SER Improvement by Radiation Hardened Latches.

Ken Yano, Takanori Hayashida, Toshinori Sato

Proceedings of the IEEE 18th Pacific Rim International Symposium on Dependable Computing, 2012

Guidelines for mitigating NBTI degradation in on-chip memories.

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida

Proceedings of the International Symposium on Communications and Information Technologies, 2012

Dynamically reducing overestimated design margin of MultiCores.

Toshinori Sato, Takanori Hayashida, Ken Yano

Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012

Importance of Single-Core Performance in the Multicore Era.

Toshinori Sato, Hideki Mori, Rikiya Yano, Takanori Hayashida

Proceedings of the Thirty-Fifth Australasian Computer Science Conference, 2012

2011

Multicore Power Management Utilizing Error-Predicting Flip-flop.

Toshinori Sato, Takahito Yoshiki, Takanori Hayashida

Proceedings of the International Conference on Complex, 2011