Hiroto Yasuura

James C. Hoe

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die V<sub>th</sub> variation.

[BibT_eX]

[DOI]

Maziar Goudarzi

Microelectron. J., 2008

A Multi-Application Smart Card System with Authentic Post-Issuance Program Modification.

[BibT_eX]

[DOI]

Mohammad Mesbah Uddin

Daisuke Ikeda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A Note on Biometrics-based Authentication with Portable Device.

[BibT_eX]

Proceedings of the SECRYPT 2008, 2008

Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption.

[BibT_eX]

[DOI]

Masanori Muroyama

Salahuddin Muhammad Salim Zabir

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

A Framework of Authentic Post-Issuance Program Modification for Multi-Application Smart Cards.

[BibT_eX]

Mohammad Mesbah Uddin

Proceedings of the 2008 International Conference on Wireless Networks, 2008

Simultaneous optimization of memory configuration and code allocation for low power embedded systems.

[BibT_eX]

[DOI]

Tadayuki Matsumura

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

A Secure High-Speed Identification Scheme for RFID Using Bloom Filters.

[BibT_eX]

[DOI]

Proceedings of the The Third International Conference on Availability, 2008

2007

A low complexity and energy efficient dynamic channel allocation algorithm for multiuser OFDM.

[BibT_eX]

[DOI]

Adil El Bourichi

Proceedings of the Wireless Telecommunications Symposium, 2007

Unlinkability and Real World Constraints in RFID Systems.

[BibT_eX]

[DOI]

Proceedings of the Fifth Annual IEEE International Conference on Pervasive Computing and Communications, 2007

A Door Access Control System with Mobile Phones.

[BibT_eX]

[DOI]

Proceedings of the Personal Wireless Communications, 2007

Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories.

[BibT_eX]

[DOI]

Yuriko Ishitobi

Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007

A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation.

[BibT_eX]

[DOI]

Maziar Goudarzi

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

On Authentication between Human and Computer.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE Conference on Pervasive Computing and Communications Workshops (PerCom 2006 Workshops), 2006

An Energy Characterization Framework for Software-Based Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, 2006

Systematic Error Detection for RFID Reliability.

[BibT_eX]

[DOI]

Daisuke Hagiwara

Proceedings of the The First International Conference on Availability, 2006

2005

Special Section on Papers Selected from AP-ASIC 2004.

[BibT_eX]

[DOI]

Shoji Kawahito

IEICE Trans. Electron., 2005

Bitwidth Optimization for Low Power Digital FIR Filter Design.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Quantitative evaluation of unlinkable ID matching schemes.

[BibT_eX]

[DOI]

Proceedings of the 2005 ACM Workshop on Privacy in the Electronic Society, 2005

Toward Unlinkable ID Management for Multi-Service Environments.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE Conference on Pervasive Computing and Communications Workshops (PerCom 2005 Workshops), 2005

A variation-aware low-power coding methodology for tightly coupled buses.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

An RFID-based multi-service system for supporting conference events.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Active Media Technology, 2005

2004

Digitally Named World: Challenges for New Social Infrastructures.

[BibT_eX]

[DOI]

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

2003

Reduction of coupling effects by optimizing the 3-D configuration of the routing grid.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Routing Methodology for Minimizing Crosstalk in SoC.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Pre-Route Power Analysis Techniques for SoC.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Variable Pipeline Depth Processor for Energy Efficient Systems.

[BibT_eX]

[DOI]

Akihiko Hyodo

Masanori Muroyama

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Leakage Power Reduction for Battery-Operated Portable Systems.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Routing methodology for minimizing 1nterconnect energy dissipation.

[BibT_eX]

[DOI]

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Towards the Digitally Named World -Challenges for New Social Infrastructures based on Information Technologies.

[BibT_eX]

[DOI]

Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits.

[BibT_eX]

[DOI]

Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

Reduction of crosstalk noise by optimizing 3-D configuration of the routing grid.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Quality-driven design by bitwidth optimization for video applications.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Quality-Driven Design for Video Applications.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Optimization of Test Accesses with a Combined BIST and External Test Scheme.

[BibT_eX]

[DOI]

Makoto Sugihara

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

A Power Minimization Technique for Arithmetic Circuits by Cell Selection.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Special Session: Security on SoC.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems.

[BibT_eX]

[DOI]

Mohammad Mesbah Uddin

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Power analysis techniques for SoC with improved wiring models.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Reducing access energy of on-chip data memory considering active data bitwidth.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

A low-power digital matched filter for spread-spectrum systems.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA.

[BibT_eX]

[DOI]

Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

2001

A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine.

[BibT_eX]

[DOI]

Genet. Program. Evolvable Mach., 2001

Software Energy Reduction Techniques for Variable-Voltage Processors.

[BibT_eX]

[DOI]

Takanori Okuma

IEEE Des. Test Comput., 2001

A system-level energy minimization approach using datapath width optimization.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000

Editorial.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2000

Flexible System LSI for Embedded Systems and Its Optimization Techniques.

[BibT_eX]

[DOI]

Akihiko Inoue

Victor M. Goulart Ferreira

Des. Autom. Embed. Syst., 2000

Functional Redundancy for Dynamic Exploitation of Performance-Energy Consumption Trade-Offs.

[BibT_eX]

[DOI]

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Variable size analysis and validation of computation quality.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

An FPGA-based genetic algorithm machine (poster abstract).

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

Analysis and Minimization of Test Time in a Combined BIST and External Test Approach.

[BibT_eX]

[DOI]

Makoto Sugihara

Hiroshi Date

Proceedings of the 2000 Design, 2000

A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

A Bus Delay Reduction Technique Considering Crosstalk.

[BibT_eX]

[DOI]

Kei Hirose

Proceedings of the 2000 Design, 2000

One language or more?: how can we design an SoC at a system level?

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

1999

Real-Time Task Scheduling for a Variable Voltage Processor.

[BibT_eX]

[DOI]

Takanori Okuma

Proceedings of the 12th International Symposium on System Synthesis, 1999

1998

Embedded System Design Using Soft-Core Processor and Valen-C.

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 1998

A novel test methodology for core-based system LSIs and a testing time minimization problem.

[BibT_eX]

[DOI]

Makoto Sugihara

Hiroshi Date

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Statistical Performance-Driven Module Binding in High-Level Synthesis.

[BibT_eX]

[DOI]

Akihiko Inoue

Proceedings of the 11th International Symposium on System Synthesis, 1998

Instruction Encoding Techniques for Area Minimization of Instruction ROM.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on System Synthesis, 1998

Voltage scheduling problem for dynamically variable voltage processors.

[BibT_eX]

[DOI]

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Instruction Scheduling for Power Reduction in Processor-Based System Design.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

Module Selection Using Manufacturing Information.

[BibT_eX]

[DOI]

Proceedings of the ASP-DAC '98, 1998

Power-Pro: Programmable Power Management Architecture.

[BibT_eX]

[DOI]

Proceedings of the ASP-DAC '98, 1998

1997

Code placement techniques for cache miss rate reduction.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1997

A High-Performance Hardware Implementation of a Survival-Based Genetic Algorithm.

[BibT_eX]

Proceedings of the Progress in Connectionist-Based Information Systems: Proceedings of the 1997 International Conference on Neural Information Processing and Intelligent Information Systems, 1997

Memory-CPU Size Optimization for Embedded System Designs.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

A HW/SW co-design environment for multi-media equipments development using inverse problem.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

1996

On the Computational Power of Binary Decision Diagram with Redundant Variables.

[BibT_eX]

[DOI]

Tetsuya Yamada

Formal Methods Syst. Des., 1996

Size-Constrained Code Placement for Cache Miss Rate Reduction.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on System Synthesis, 1996

Basic experimentation on accuracy of power estimation for CMOS VLSI circuits.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Optimal Code Placement of Embedded Software for Instruction Caches.

[BibT_eX]

[DOI]

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Foreword.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 1995

A Proposal for a Co-design Method in Control Systems Using Combination of Models.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 1995

1994

Design Reuse: Fact or Fiction? (Panel).

[BibT_eX]

[DOI]

Proceedings of the 31st Conference on Design Automation, 1994

1993

A Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking.

[BibT_eX]

[DOI]

Proceedings of the 7th international conference on Supercomputing, 1993

1992

Design of data-path module generators from algorithmic representations.

[BibT_eX]

Vasily G. Moshnyaga

Keikichi Tamaru

Proceedings of the Synthesis for Control Dominated Circuits, 1992

1990

Formal semantics of UDL/I and its applications to CAD/DA tools.

[BibT_eX]

[DOI]

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Extraction of Functional Information from Combinatorial Circuits.

[BibT_eX]

[DOI]

M. Ohmura

Keikichi Tamaru

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I.

[BibT_eX]

[DOI]

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

Semantics of a Hardware Design Language for Japanese Standardization.

[BibT_eX]

[DOI]

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Locally Computable Coding for Unary Operations.

[BibT_eX]

[DOI]

Proceedings of the Concurrency: Theory, 1989

1987

High-Speed Logic Simulation on Vector Processors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

On high-speed parallel algorithms using redundant coding.

[BibT_eX]

[DOI]

Naofumi Takagi

Syst. Comput. Jpn., 1987

1985

High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree.

[BibT_eX]

[DOI]

Naofumi Takagi

IEEE Trans. Computers, 1985

1984

Hardware Algorithms for VLSI Systems.

[BibT_eX]

[DOI]

Proceedings of the VLSI Engineering: Beyond Software Engineering, 1984

On Parallel Computational Complexity of Unification.

[BibT_eX]

Proceedings of the International Conference on Fifth Generation Computer Systems, 1984

1982

The Parallel Enumeration Sorting Scheme for VLSI.

[BibT_eX]

[DOI]

Naofumi Takagi

IEEE Trans. Computers, 1982

Hardware Algorithms and Logic Design Automation. An Overview and Progress Report.

[BibT_eX]

[DOI]

Proceedings of the RIMS Symposium on Software Science and Engineering, 1982

An Interactive Simulation System for structured logic design - ISS.

[BibT_eX]

[DOI]

Proceedings of the 19th Design Automation Conference, 1982

1981

Width and Depth of Combinational Logic Circuits.

[BibT_eX]

[DOI]