Takashi Morimoto

According to our database1, Takashi Morimoto authored at least 12 papers between 2004 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Learning Occlusion-Aware Dense Correspondences for Multi-Modal Images.
Proceedings of the 18th IEEE International Conference on Advanced Video and Signal Based Surveillance, 2022

2021
Autonomous Human-Following Drone for Monitoring a Pedestrian from Constant Distance and Direction.
Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

2019
Motion Capture System by Spatio-Temporal Integration of Multiple Kinects.
Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

2018
Gaze and body capture system under VR experiences.
Proceedings of the 24th ACM Symposium on Virtual Reality Software and Technology, 2018

2006
Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation.
IEICE Trans. Inf. Syst., 2006

Multi-object tracking VLSI architecture using image-scan based region growing and feature matching.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Object tracking in video pictures based on image segmentation and pattern matching.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A low-power video segmentation LSI with boundary-active-only architecture.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation.
IEICE Trans. Inf. Syst., 2004

350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004


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