Tetsushi Koide
According to our database1,
Tetsushi Koide
authored at least 106 papers
between 1992 and 2022.
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Bibliography
2022
Classification with CNN features and SVM on Embedded DSP Core for Colorectal Magnified NBI Endoscopic Video Image.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022
Feasibility Study for Computer-Aided Diagnosis System with Navigation Function of Clear Region for Real-Time Endoscopic Video Image on Customizable Embedded DSP Cores.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022
2021
A Hardware Implementation on Customizable Embedded DSP Core for Colorectal Tumor Classification with Endoscopic Video toward Real-Time Computer-Aided Diagnosais System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
An Image Segmentation Method for Automatic Analysis of Skin Surface Structure in Atopic Dermatitis by the Impression Mold Technique.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Sweat Droplets Detection Using Image Segmentation on Skin Surface for Evaluation of Sweating Responses to Thermal Stimulus in Atopic Dermatitis.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
2020
Classification Method with CNN features and SVM for Computer-Aided Diagnosis System in Colorectal Magnified NBI Endoscopy.
Proceedings of the 2020 IEEE Region 10 Conference, 2020
Acceleration of arithmetic processing with CAM-based massive-parallel SIMD matrix core.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
2019
Feature Extraction of Colorectal Endoscopic Images for Computer-Aided Diagnosis with CNN.
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019
Structuring Element-counting Approach for Morphological Pattern Spectrum-based Image Manipulation Detection.
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019
A Hardware Implementation of Colorectal Tumor Classification for Endoscopic Video on Customizable DSP Toward Real-Time Computer-Aided Diagnosis System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
An Image Analysis Method for Lettuce Leaf and Root Growth Analysis in Hydroponic Culture.
Proceedings of the TENCON 2018, 2018
Implementation of Computer-Aided Diagnosis System on Customizable DSP Core for Colorectal Endoscopic Images with CNN Features and SVM.
Proceedings of the TENCON 2018, 2018
2016
Domain Adaptation with L2 constraints for classifying images from different endoscope systems.
CoRR, 2016
CoRR, 2016
Development of a Real-time Colorectal Tumor Classification System for Narrow-band Imaging zoom-videoendoscopy.
CoRR, 2016
Corrigendum to "Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition" [Artif. Intell. Med. 68 (March 2016) 1-16].
Artif. Intell. Medicine, 2016
Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition.
Artif. Intell. Medicine, 2016
Proceedings of the Computer Vision - ACCV 2016 Workshops, 2016
2015
Trade-off between speed and performance for colorectal endoscopic NBI image classification.
Proceedings of the Medical Imaging 2015: Image Processing, 2015
Transfer learning for Bag-of-Visual words approach to NBI endoscopic image classification.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
Image segmentation of pyramid style identifier based on Support Vector Machine for colorectal endoscopic images.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
2014
Compact hardware oriented number recognition algorithm for real-time speed traffic-sign recognition.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
FPGA implementation of feature extraction for colorectal endoscopic images with NBI magnification.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Pipeline scanning architecture with computation reduction for rectangle pattern matching in real-time traffic sign detection.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014
Interleaved-bitslice AES encryption and decryption with massive-parallel mobile embedded processor.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
FPGA implementation of type identifier for colorectal endoscopie images with NBI magnification.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
Smoothing posterior probabilities with a particle filter of dirichlet distribution for stabilizing colorectal NBI endoscopy recognition.
Proceedings of the IEEE International Conference on Image Processing, 2013
Power electronics education using the integrated circuit consistent education system and TCAD.
Proceedings of the IEEE Frontiers in Education Conference, 2013
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013
2012
IEEE J. Solid State Circuits, 2012
A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching.
IEICE Trans. Inf. Syst., 2012
2011
IEEE J. Solid State Circuits, 2011
Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems.
IEICE Trans. Inf. Syst., 2011
An associative memory-based learning model with an efficient hardware implementation in FPGA.
Expert Syst. Appl., 2011
Proceedings of the 2011 IEEE International Conference on Robotics and Biomimetics, 2011
2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size.
Proceedings of the First International Conference on Networking and Computing, 2010
Optimization Vector Quantization by Adaptive Associative-Memory-Based Codebook Learning in Combination with Huffman Coding.
Proceedings of the First International Conference on Networking and Computing, 2010
Low-power word-parallel nearest-Hamming-distance search circuit based on frequency mapping.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2008
Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor.
IEICE Trans. Electron., 2008
2007
Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer.
IEICE Trans. Inf. Syst., 2007
Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory.
IEICE Trans. Inf. Syst., 2007
Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor.
IEICE Trans. Inf. Syst., 2007
4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words.
IEICE Trans. Electron., 2007
Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin.
IEICE Electron. Express, 2007
Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2006
IEICE Trans. Electron., 2006
Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation.
IEICE Trans. Inf. Syst., 2006
Multi-object tracking VLSI architecture using image-scan based region growing and feature matching.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA.
Proceedings of the IEEE International Conference on Evolutionary Computation, 2006
Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
Syst. Comput. Jpn., 2005
A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture.
IEEE J. Solid State Circuits, 2005
IEICE Trans. Electron., 2005
A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features.
IEICE Trans. Electron., 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example].
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the Advanced Video and Signal Based Surveillance, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation.
IEICE Trans. Inf. Syst., 2004
Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
A nearest-hamming-distance search memory with fully parallel mixed digital-analog match circuitry.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time.
Syst. Comput. Jpn., 2002
Compact associative-memory architecture with fully parallel search capability for the minimum Hamming distance.
IEEE J. Solid State Circuits, 2002
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
2001
Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual.
Syst. Comput. Jpn., 2001
Discret. Appl. Math., 2001
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer.
Proceedings of ASP-DAC 2000, 2000
1999
A timing-driven floorplanning algorithm with the Elmore delay model for building block layout.
Integr., 1999
An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
1998
Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm.
Proceedings of the Parallel Problem Solving from Nature, 1998
A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout.
Proceedings of the ASP-DAC '98, 1998
1997
Integr., 1997
Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
A new performance driven placement method with the Elmore delay model for row based VLSIs.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
A new system partitioning method under performance and physical constraints for multi-chip modules.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
1993
Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Proceedings of the European Design Automation Conference 1993, 1993
1992
Proceedings of the conference on European design automation, 1992