Tetsushi Koide

According to our database1, Tetsushi Koide authored at least 92 papers between 1992 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2019
Feature Extraction of Colorectal Endoscopic Images for Computer-Aided Diagnosis with CNN.
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

Development of In-situ Monitoring System for Crop Growth Observation.
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

Low Cost and Robust Field-Deployable Environmental Sensor for Smart Agriculture.
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

Structuring Element-counting Approach for Morphological Pattern Spectrum-based Image Manipulation Detection.
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

An IoT-gateway with the information-centric communication.
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

A Hardware Implementation of Colorectal Tumor Classification for Endoscopic Video on Customizable DSP Toward Real-Time Computer-Aided Diagnosis System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
An Image Analysis Method for Lettuce Leaf and Root Growth Analysis in Hydroponic Culture.
Proceedings of the TENCON 2018, 2018

Implementation of Computer-Aided Diagnosis System on Customizable DSP Core for Colorectal Endoscopic Images with CNN Features and SVM.
Proceedings of the TENCON 2018, 2018

2016
Domain Adaptation with L2 constraints for classifying images from different endoscope systems.
CoRR, 2016

Computer-Aided Colorectal Tumor Classification in NBI Endoscopy Using CNN Features.
CoRR, 2016

Transfer Learning for Endoscopic Image Classification.
CoRR, 2016

Development of a Real-time Colorectal Tumor Classification System for Narrow-band Imaging zoom-videoendoscopy.
CoRR, 2016

Corrigendum to "Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition" [Artif. Intell. Med. 68 (March 2016) 1-16].
Artificial Intelligence in Medicine, 2016

Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition.
Artificial Intelligence in Medicine, 2016

Discriminative Subtree Selection for NBI Endoscopic Image Labeling.
Proceedings of the Computer Vision - ACCV 2016 Workshops, 2016

2015
Trade-off between speed and performance for colorectal endoscopic NBI image classification.
Proceedings of the Medical Imaging 2015: Image Processing, 2015

Transfer learning for Bag-of-Visual words approach to NBI endoscopic image classification.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

Image segmentation of pyramid style identifier based on Support Vector Machine for colorectal endoscopic images.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

2014
Compact hardware oriented number recognition algorithm for real-time speed traffic-sign recognition.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

FPGA implementation of feature extraction for colorectal endoscopic images with NBI magnification.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Pipeline scanning architecture with computation reduction for rectangle pattern matching in real-time traffic sign detection.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

SVM-MRF segmentation of colorectal NBI endoscopic images.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

Interleaved-bitslice AES encryption and decryption with massive-parallel mobile embedded processor.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

FPGA implementation of type identifier for colorectal endoscopie images with NBI magnification.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Low cost hardware implementation for traffic sign detection system.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
Smoothing posterior probabilities with a particle filter of dirichlet distribution for stabilizing colorectal NBI endoscopy recognition.
Proceedings of the IEEE International Conference on Image Processing, 2013

Power electronics education using the integrated circuit consistent education system and TCAD.
Proceedings of the IEEE Frontiers in Education Conference, 2013

Labeling colorectal NBI zoom-videoendoscope image sequences with MRF and SVM.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

2012
Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping.
J. Solid-State Circuits, 2012

A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching.
IEICE Transactions, 2012

2011
A Scalable Massively Parallel Processor for Real-Time Image Processing.
J. Solid-State Circuits, 2011

Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems.
IEICE Transactions, 2011

An associative memory-based learning model with an efficient hardware implementation in FPGA.
Expert Syst. Appl., 2011

Real-time hybrid learning and recognition system with software-hardware cooperation.
Proceedings of the 2011 IEEE International Conference on Robotics and Biomimetics, 2011

2010
Measurement-Based Ring Oscillator Variation Analysis.
IEEE Design & Test of Computers, 2010

A scalable massively parallel processor for real-time image processing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size.
Proceedings of the First International Conference on Networking and Computing, 2010

Optimization Vector Quantization by Adaptive Associative-Memory-Based Codebook Learning in Combination with Huffman Coding.
Proceedings of the First International Conference on Networking and Computing, 2010

2008
Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor.
IEICE Transactions, 2008

2007
Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer.
IEICE Transactions, 2007

Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory.
IEICE Transactions, 2007

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor.
IEICE Transactions, 2007

4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words.
IEICE Transactions, 2007

Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories.
IEICE Transactions, 2007

A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin.
IEICE Electronic Express, 2007

Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC.
IEICE Transactions, 2006

Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation.
IEICE Transactions, 2006

Multi-object tracking VLSI architecture using image-scan based region growing and feature matching.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA.
Proceedings of the IEEE International Conference on Evolutionary Computation, 2006

Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Application of Multi-ported CAM for Parallel Coding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Chip size and performance evaluations of shared cache for on-chip multiprocessor.
Systems and Computers in Japan, 2005

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh.
IEICE Transactions, 2005

A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features.
IEICE Transactions, 2005

Design of superscalar processor with multi-bank register file.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Object tracking in video pictures based on image segmentation and pattern matching.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example].
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A parallel hardware design for parametric active contour models.
Proceedings of the Advanced Video and Signal Based Surveillance, 2005

A low-power video segmentation LSI with boundary-active-only architecture.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation.
IEICE Transactions, 2004

Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
A nearest-hamming-distance search memory with fully parallel mixed digital-analog match circuitry.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time.
Systems and Computers in Japan, 2002

2001
Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual.
Systems and Computers in Japan, 2001

Topological optimization with a network reliability constraint.
Discrete Applied Mathematics, 2001

2000
Genetic algorithm accelerator GAA-II.
Proceedings of ASP-DAC 2000, 2000

Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer.
Proceedings of ASP-DAC 2000, 2000

1999
A timing-driven floorplanning algorithm with the Elmore delay model for building block layout.
Integration, 1999

An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998
Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm.
Proceedings of the Parallel Problem Solving from Nature, 1998

A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout.
Proceedings of the ASP-DAC '98, 1998

1997
A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs.
Integration, 1997

Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Pin assignment with global routing for VLSI building block layout.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

A three-layer over-the-cell multi-channel router for a new cell model.
Integration, 1996

1995
A Verification Algorithm for Logic Circuits with Internal Variables.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

An MCM Routing Algorithm Considering Crosstalk.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A three-layer over-cell multi-channel routing method for a new cell model.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

A new performance driven placement method with the Elmore delay model for row based VLSIs.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

A new system partitioning method under performance and physical constraints for multi-chip modules.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
A Systolic Graph Partitioning Algorithm for VLSI Design.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Floorplanning Method with Topological Constraint Manipulation.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A new global routing algorithm for over-the-cell routing in standard cell layouts.
Proceedings of the European Design Automation Conference 1993, 1993

1992
An optimal channel pin assignment with multiple intervals for building block layout.
Proceedings of the conference on European design automation, 1992


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