Hans Jürgen Mattausch

According to our database1, Hans Jürgen Mattausch authored at least 92 papers between 2000 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2019
Power Reduction and BTI Mitigation of Data-Cache Memory Based on the Storage Management of Narrow-Width Values.
IEEE Trans. VLSI Syst., 2019

Prevention of Highly Power-Efficient Circuits due to Short-Channel Effects in MOSFETs.
IEICE Transactions, 2019

Energy-Efficient Hardware Implementation of Road-Lane Detection Based on Hough Transform with Parallelized Voting Procedure and Local Maximum Algorithm.
IEICE Transactions, 2019

A Hardware-Efficient Recognition Accelerator Using Haar-Like Feature and SVM Classifier.
IEEE Access, 2019

Surface-Property Recognition With Force Sensors for Stable Walking of Humanoid Robot.
IEEE Access, 2019

Analysis of Embedded-Diode Performance in MOSFET under Switching Condition.
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

Analysis of IGBT Charging/Discharging Mechanism for Accurate Compact Modeling.
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

Power Consumption Estimation of Biped Robot During Walking.
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

Validation on Duality in Impact-ionization Carrier Generation at the Onset of Snapback in Power MOSFETs.
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

Stability Analysis of Humanoid Robots with Gyro Sensors Subjected to External Push Forces.
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

2018
Resource-Efficient Object-Recognition Coprocessor With Parallel Processing of Multiple Scan Windows in 65-nm CMOS.
IEEE Trans. VLSI Syst., 2018

A Hardware Architecture for Cell-Based Feature-Extraction and Classification Using Dual-Feature Space.
IEEE Trans. Circuits Syst. Video Techn., 2018

A Modular and Reconfigurable Pipeline Architecture for Learning Vector Quantization.
IEEE Trans. on Circuits and Systems, 2018

Compact modeling of dynamic trap density evolution for predicting circuit-performance aging.
Microelectronics Reliability, 2018

Self-controlled walking robot with gyro sensor network for stable movement on non-smooth surfaces.
Proceedings of the 2018 IEEE International Conference on Simulation, 2018

Compact Modeling for Power Efficient Circuit Design.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

2017
Real-Time Straight-Line Detection for XGA-Size Videos by Hough Transform with Parallelized Voting Procedures.
Sensors, 2017

Modeling of Field-Plate Effect on Gallium-Nitride-Based High Electron Mobility Transistors for High-Power Applications.
IEICE Transactions, 2017

Modeling of dynamic trap density increase for aging simulation of any MOSFET circuits.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

Compact modeling approach for electro-mechanical system simulation.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
A Memory-Based Modular Architecture for SOM and LVQ with Dynamic Configuration.
IEEE Trans. Multi-Scale Computing Systems, 2016

Efficiency Analysis of SiC-MOSFET-Based Bidirectional Isolated DC/DC Converters.
IEICE Transactions, 2016

Actuator-Control Circuit Based on OTFTs and Flow-Rate Estimation for an All-Organic Fluid Pump.
IEICE Transactions, 2016

k Nearest Neighbor Classification Coprocessor with Weighted Clock-Mapping-Based Searching.
IEICE Transactions, 2016

Dynamically reconfigurable system for LVQ-based on-chip learning and recognition.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Pixel-based pipeline hardware architecture for high-performance Haar-like feature extraction.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Mixed-domain compact modeling framework for fluid flow driven by electrostatic organic actuators.
Proceedings of the 45th European Solid State Device Research Conference, 2015

Word-parallel associative memory for k-nearest-neighbor with configurable storage space of reference vectors.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
Compact Modeling of Injection Enhanced Insulated Gate Bipolar Transistor Valid for Optimization of Switching Frequency.
IEICE Transactions, 2014

Memory-based hardware-accelerated system for high-speed human detection.
Advanced Robotics, 2014

A SoPC architecture for nearest-neighbor based learning and recognition.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2014

A coprocessor for clock-mapping-based nearest Euclidean distance search with feature vector dimension adaptability.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

LVQ neural network SoC adaptable to different on-chip learning and recognition applications.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
K-means clustering algorithm for multimedia applications with flexible HW/SW co-design.
Journal of Systems Architecture - Embedded Systems Design, 2013

Modeling of NBTI Stress Induced Hole-Trapping and Interface-State-Generation Mechanisms under a Wide Range of Bias Conditions.
IEICE Transactions, 2013

Modeling of Trench-Gate Type HV-MOSFETs for Circuit Simulation.
IEICE Transactions, 2013

2012
Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping.
J. Solid-State Circuits, 2012

Compact Modeling of Expansion Effects in LDMOS.
IEICE Transactions, 2012

A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching.
IEICE Transactions, 2012

Human recognition with a hardware-accelerated multi-prototype learning and classification system.
Proceedings of the 2012 IEEE International Conference on Robotics and Biomimetics, 2012

Cluster-Based Prototype Learning System for Multiple Applications with Flexible HW/SW Codesign.
Proceedings of the 13th International Conference on Parallel and Distributed Computing, 2012

Digital associative memory for word-parrallel Manhattan-distance-based vector quantization.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
A Scalable Massively Parallel Processor for Real-Time Image Processing.
J. Solid-State Circuits, 2011

Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100 nm SOC Circuit Design.
IEICE Transactions, 2011

Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems.
IEICE Transactions, 2011

An associative memory-based learning model with an efficient hardware implementation in FPGA.
Expert Syst. Appl., 2011

Real-time hybrid learning and recognition system with software-hardware cooperation.
Proceedings of the 2011 IEEE International Conference on Robotics and Biomimetics, 2011

2010
Measurement-Based Ring Oscillator Variation Analysis.
IEEE Design & Test of Computers, 2010

A scalable massively parallel processor for real-time image processing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size.
Proceedings of the First International Conference on Networking and Computing, 2010

Optimization Vector Quantization by Adaptive Associative-Memory-Based Codebook Learning in Combination with Huffman Coding.
Proceedings of the First International Conference on Networking and Computing, 2010

2009
Degraded Frequency-Tuning Range and Oscillation Amplitude of LC-VCOs due to the Nonquasi-Static Effect in MOS Varactors.
IEICE Transactions, 2009

Non-Quasi-Static Carrier Dynamics of MOSFETs under Low-Voltage Operation.
IEICE Transactions, 2009

2008
Non-quasi-static approach with surface-potential-based MOSFET model HiSIM for RF circuit simulations.
Mathematics and Computers in Simulation, 2008

Compact Double-Gate Metal-Oxide-Semiconductor Field Effect Transistor Model for Device/Circuit Optimization.
IEICE Transactions, 2008

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor.
IEICE Transactions, 2008

The Physics and Modeling of Mosfets - Surface-Potential Model HiSIM
International Series on Advances in Solid State Electronics and Technology, World Scientific, ISBN: 978-981-4477-57-4, 2008

2007
Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer.
IEICE Transactions, 2007

Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory.
IEICE Transactions, 2007

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor.
IEICE Transactions, 2007

4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words.
IEICE Transactions, 2007

Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories.
IEICE Transactions, 2007

A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin.
IEICE Electronic Express, 2007

Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC.
IEICE Transactions, 2006

Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation.
IEICE Transactions, 2006

Multi-object tracking VLSI architecture using image-scan based region growing and feature matching.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA.
Proceedings of the IEEE International Conference on Evolutionary Computation, 2006

Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Application of Multi-ported CAM for Parallel Coding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Chip size and performance evaluations of shared cache for on-chip multiprocessor.
Systems and Computers in Japan, 2005

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh.
IEICE Transactions, 2005

A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential.
IEICE Transactions, 2005

1/f-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation.
IEICE Transactions, 2005

A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features.
IEICE Transactions, 2005

Design of superscalar processor with multi-bank register file.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Object tracking in video pictures based on image segmentation and pattern matching.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example].
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

MOSFET harmonic distortion analysis up to the non-quasi-static frequency regime.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

A parallel hardware design for parametric active contour models.
Proceedings of the Advanced Video and Signal Based Surveillance, 2005

A low-power video segmentation LSI with boundary-active-only architecture.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation.
IEICE Transactions, 2004

Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
A nearest-hamming-distance search memory with fully parallel mixed digital-analog match circuitry.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Temperature-independence-point properties for 0.1μm-scale pocket-implant technologies and the impact on circuit design.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2001
Correlation method of circuit-performance and technology fluctuations for improved design reliability.
Proceedings of ASP-DAC 2001, 2001

2000
High performance of short-channel MOSFETs due to an elevated central-channel doping.
Proceedings of ASP-DAC 2000, 2000


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