Tasuku Nishihara

According to our database1, Tasuku Nishihara authored at least 12 papers between 2005 and 2011.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2011
Multi-Level Bounded Model Checking with Symbolic Counterexamples.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

2010
Performance Estimation with Automatic False-Path Detection for System-Level Designs.
IPSJ Trans. Syst. LSI Des. Methodol., 2010

Synthesis and formal verification of on-chip protocol transducers through decomposed specification.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009
Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath.
IEICE Trans. Inf. Syst., 2009

A Post-Silicon Debug Support Using High-Level Design Description.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Multi-level Bounded Model Checking to detect bugs beyond the bound.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

An Interactive Verification and Debugging Environment by Concrete/Symbolic Simulations for System-Level Designs.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
Hardware/Software Co-design and Verification Methodology from System Level Based on System Dependence Graph.
J. Univers. Comput. Sci., 2007

Development and Verification of a Collaborative Printing Environment.
Proceedings of the Fifth International Conference on Creating, 2007

2006
Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

System LSI distributed collaborative design environment for both designers and CAD developers/engineers.
Proceedings of the Fourth International Conference on Creating, 2006

2005
Slicing-based Hardware/Software Co-design Methodology From Functional Specifications.
Proceedings of the First IPM International Workshop on Foundations of Software Engineering, 2005


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