Takeshi Matsumoto
Orcid: 0000-0003-4799-7963
According to our database1,
Takeshi Matsumoto
authored at least 41 papers
between 2003 and 2019.
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Bibliography
2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
In-line Optical Amplification for Silicon Photonics Platform by Flip-Chip Bonded InP-SOAs.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018
Lossless Operation of SOA-Integrated Silicon Photonics Switch for 8 × 32-Gbaud 16-QAM WDM Signals.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018
2017
Effect of low-intensity whole-body vibration on bone defect repair and associated vascularization in mice.
Medical Biol. Eng. Comput., 2017
Experimental Study of Ankle Joint Pushing Mechanism Concerning About the Horizontal Movement of Talus.
J. Robotics Mechatronics, 2017
Pulmonary kinematic analysis with non-rigid deformable registration for detecting localised emphysema.
Comput. methods Biomech. Biomed. Eng. Imaging Vis., 2017
Motion recognition by natural language including success and failure of tasks for co-working robot with human.
Proceedings of the IEEE International Conference on Advanced Intelligent Mechatronics, 2017
2016
In-line optical amplification for Si waveguides on 1×8 splitter and selector by flip-chip bonded InP-SOAs.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016
2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Proposal of an ankle joint bending machine using exoskeleton support from foot to hip.
Proceedings of the 2015 IEEE International Conference on Robotics and Biomimetics, 2015
2014
SAT-based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions.
IPSJ Trans. Syst. LSI Des. Methodol., 2014
Flip-chip-bonded, 8-wavelength AlGaInAs DFB laser array operable up to 70°C for silicon WDM interconnects.
Proceedings of the European Conference on Optical Communication, 2014
2013
Debugging Methods Through Identification of Appropriate Functions for Internal Gates.
Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Hardware implementation of BLTL property checkers for acceleration of statistical model checking.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Fast simulation of Digital Spiking Silicon Neuron model employing reconfigurable dataflow computing.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013
Rectification of advanced microprocessors without changing routing on FPGAs (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013
2012
An efficient method to localize and correct bugs in high-level designs using counterexamples and potential dependence.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
2011
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
IPSJ Trans. Syst. LSI Des. Methodol., 2010
Synthesis and formal verification of on-chip protocol transducers through decomposed specification.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the International Joint Conference on Neural Networks, 2010
Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging.
Proceedings of the 28th International Conference on Computer Design, 2010
2009
Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath.
IEICE Trans. Inf. Syst., 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
2008
A HW/SW Co-Reuse Methodology Based on Design Refinement Templates in UML Diagrams.
Proceedings of the ICSOFT 2008, 2008
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008
An Interactive Verification and Debugging Environment by Concrete/Symbolic Simulations for System-Level Designs.
Proceedings of the 17th IEEE Asian Test Symposium, 2008
2007
Proceedings of the Fifth International Conference on Creating, 2007
2006
Math. Comput. Simul., 2006
Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 2006 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2006
Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006
2005
An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
2003
Proceedings of the Australasian Language Technology Workshop, 2003