Teruhiko Yamada

According to our database, Teruhiko Yamada authored at least 18 papers between 1983 and 1999.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1999

Identification of Redundant Crosspoint Faults in Sequential PLAs with Fault-Free Hardware Reset.

Teruhiko Yamada, Toshinori Kotake, Hiroshi Takahashi, Koji Yamazaki

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

1997 Asian Test Symposium.

Teruhiko Yamada

IEEE Des. Test Comput., 1998

On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates.

Teruhiko Yamada, Tsuneto Hanashima, Yasuhiro Suemori, Masaaki Maezawa

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

An approach to diagnose logical faults in partially observable sequential circuits.

Koji Yamazaki, Teruhiko Yamada

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996

On Current Testing of Josephson Logic Circuits Using the 4JL Gate Family.

Teruhiko Yamada, Tsuyoshi Sasaki

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995

A Single Bridging Fault Location Technique for CMOS Combinational Circuits.

Koji Yamazaki, Teruhiko Yamada

IEICE Trans. Inf. Syst., 1995

Accelerating the Pace of R&D in Asia.

Teruhiko Yamada

IEEE Des. Test Comput., 1995

A simple technique for locating gate-level faults in combinational circuits.

Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1992

A method of diagnosing single stuck-at faults in combinational circuits.

Teruhiko Yamada, Yoshiyuki Nakamura

Syst. Comput. Jpn., 1992

1991

Method of diagnosing single bridging faults in combinational circuit.

Teruhiko Yamada, Koji Yamazaki

Syst. Comput. Jpn., 1991

Method of diagnosing multiple stuck-at-faults in combinational circuits.

Teruhiko Yamada, Shuji Hamada, Tatsuo Matsumoto, Toshihiko Takahashi, Takao Nakayama

Syst. Comput. Jpn., 1991

1990

Pseudorandom pattern built-in self-test for embedded rams.

Teruhiko Yamada, Hiroshi Nakajima

Syst. Comput. Jpn., 1990

1988

Test research in Japan.

Hideo Fujiwara, Yuzo Takamatsu, Takashi Nanya, Teruhiko Yamada, Hideo Tamamoto, Kiyoshi Furuya

IEEE Des. Test, 1988

1986

Syndrome-testable design and syndrome computing method for large PLA's.

Teruhiko Yamada

Syst. Comput. Jpn., 1986

1985

PLAYER: a PLA design system for VLSI's.

Yoshiyuki Koseki, Teruhiko Yamada

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1984

Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults.

Teruhiko Yamada, Takashi Nanya

IEEE Trans. Computers, 1984

1983

Comments on "Detection Location of Input and Feedback Bridging Faults Among Input Output Lines".

Teruhiko Yamada, Takashi Nanya

IEEE Trans. Computers, 1983

Syndrome-Testable Design of Programmable Logic Arrays.

Teruhiko Yamada

Proceedings of the Proceedings International Test Conference 1983, 1983