Teruhiko Yamada

According to our database1, Teruhiko Yamada authored at least 17 papers between 1983 and 1999.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

1999
Identification of Redundant Crosspoint Faults in Sequential PLAs with Fault-Free Hardware Reset.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998
1997 Asian Test Symposium.
IEEE Des. Test Comput., 1998

On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
An approach to diagnose logical faults in partially observable sequential circuits.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
On Current Testing of Josephson Logic Circuits Using the 4JL Gate Family.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995
A Single Bridging Fault Location Technique for CMOS Combinational Circuits.
IEICE Trans. Inf. Syst., 1995

Accelerating the Pace of R&D in Asia.
IEEE Des. Test Comput., 1995

A simple technique for locating gate-level faults in combinational circuits.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1992
A method of diagnosing single stuck-at faults in combinational circuits.
Systems and Computers in Japan, 1992

1991
Method of diagnosing single bridging faults in combinational circuit.
Systems and Computers in Japan, 1991

Method of diagnosing multiple stuck-at-faults in combinational circuits.
Systems and Computers in Japan, 1991

1990
Pseudorandom pattern built-in self-test for embedded rams.
Systems and Computers in Japan, 1990

1986
Syndrome-testable design and syndrome computing method for large PLA's.
Systems and Computers in Japan, 1986

1985
PLAYER: a PLA design system for VLSI's.
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1984
Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults.
IEEE Trans. Computers, 1984

1983
Comments on "Detection Location of Input and Feedback Bridging Faults Among Input Output Lines".
IEEE Trans. Computers, 1983

Syndrome-Testable Design of Programmable Logic Arrays.
Proceedings of the Proceedings International Test Conference 1983, 1983


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