Tetsuro Okura

According to our database, Tetsuro Okura authored at least 5 papers between 2006 and 2013.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2013

A low-power technique for pipelined ADCs with programmable gain amplification.

Tetsuro Okura, Shunsuke Okura, Toshimasa Matsuoka, Kenji Taniguchi

IEICE Electron. Express, 2013

2010

A Frequency Model of a Continuously Driven Clocked CMOS Comparator.

Shunsuke Okura, Hajime Shibata, Tetsuro Okura, Toru Ido, Kenji Taniguchi

IEEE Trans. Circuits Syst. II Express Briefs, 2010

2009

A Reference Voltage Buffer with Settling Boost Technique for a 12 bit 18 MHz Multibit/Stage Pipelined A/D Converter.

Shunsuke Okura, Tetsuro Okura, Toru Ido, Kenji Taniguchi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

2007

A 10-bit 800-Column Low-Power RAM Bank Including Energy-Efficient D-Flip-Flops for a Column-Parallel ADC.

Shunsuke Okura, Tetsuro Okura, Indika U. K. Bogoda Appuhamylage, Kenji Taniguchi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2006

Frequency Response Analysis of Latch Utilized in High-Speed Comparator.

Shunsuke Okura, Tetsuro Okura, Kenji Taniguchi, Hajime Shibata

Proceedings of the 13th IEEE International Conference on Electronics, 2006