Hajime Shibata

Orcid: 0000-0001-5333-4619

According to our database1, Hajime Shibata authored at least 29 papers between 2000 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET.
IEEE J. Solid State Circuits, April, 2024

22.2 A 700MHZ-BW -164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 3 using Digital Cancellation of DAC Errors.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
A 1-MHz-Bandwidth Continuous-Time Delta-Sigma ADC Achieving >90dB SFDR and >80dB Antialiasing Using Reference-Switched Resistive Feedback DACs.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2021
Continuous-Time Pipelined Analog-to-Digital Converters: A Mini-Tutorial.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020
16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2018
A -89-dBc IMD3 DAC Sub-System in a 465-MHz BW CT Delta-Sigma ADC Using a Power and Area Efficient Calibration Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers.
IEEE J. Solid State Circuits, 2018

Thermal noise limits - ΔΣ vs. pipeline ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164-dBFS/Hz NSD.
IEEE J. Solid State Circuits, 2017

High-speed oversampled continuous-time analog-to-digital converters.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

16.2 A 9GS/s 1GHz-BW oversampled continuous-time pipeline ADC achieving -161dBFS/Hz NSD.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A LTE RX front-end with digitally programmable multi-band blocker cancellation in 28nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

Adaptive digital noise-cancellation filtering using cross-correlators for continuous-time MASH ADC in 28nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS.
IEEE J. Solid State Circuits, 2016

15.5 A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014
Advances in high-speed continuous-time delta-sigma modulators.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2012
A DC-to-1 GHz Tunable RF Delta Sigma ADC Achieving DR = 74 dB and BW = 150 MHz at f<sub>0</sub> = 450 MHz Using 550 mW.
IEEE J. Solid State Circuits, 2012

A DC-to-1GHz tunable RF ΔΣ ADC achieving DR = 74dB and BW = 150MHz at f0 = 450MHz using 550mW.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2010
A Frequency Model of a Continuously Driven Clocked CMOS Comparator.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

2008
A 100mW 10MHz-BW CT ΔΣ Modulator with 87dB DR and 91dBc IMD.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
Measurement System for Switching Current Distribution in Intrinsic Josephson Junctions.
IEICE Trans. Electron., 2007

2006
A 375-mW Quadrature Bandpass$\Delta\Sigma$ADC With 8.5-MHz BW and 90-dB DR at 44 MHz.
IEEE J. Solid State Circuits, 2006

A 375mW Quadrature Bandpass ΔΣ ADC with 90dB DR and 8.5MHz BW at 44MHz.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Frequency Response Analysis of Latch Utilized in High-Speed Comparator.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2004
Controllable decoding for automated analog circuit structure design.
Soft Comput., 2004

2003
Automated Design of Analog Circuits Using a Cell-Based Structure.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

2001
Analog circuit synthesis by superimposing of sub-circuits.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Maintenance of location-dependent views in mobile database environments.
Syst. Comput. Jpn., 2000


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