Thomas A. Hughes

According to our database, Thomas A. Hughes authored at least 7 papers between 1990 and 1994.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1994

A 250-MHz wave pipelined adder in 2-μm CMOS.

Wentai Liu, C. Thomas Gray, David Fan, William J. Farlow, Thomas A. Hughes, Ralph K. Cavin III

IEEE J. Solid State Circuits, September, 1994

A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution.

C. Thomas Gray, Wentai Liu, Wilhelmus A. M. Van Noije, Thomas A. Hughes, Ralph K. Cavin III

IEEE J. Solid State Circuits, March, 1994

1993

Fast Algorithms for One-Dimensional Compaction with Jog Insertion.

Matthias F. M. Stallmann, Thomas A. Hughes

Proceedings of the Algorithms and Data Structures, Third Workshop, 1993

1991

Theoretical and Practical Issues in CMOS Wave Pipelining.

C. Thomas Gray, Thomas A. Hughes, Sanjay Arora, Wentai Liu, Ralph K. Cavin III

Proceedings of the VLSI 91, 1991

1990

Unconstrained via minimization for topological multilayer routing.

Matthias F. M. Stallmann, Thomas A. Hughes, Wentai Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

P³A: a partitionable parallel/pipeline architecture for real-time image processing.

C. Thomas Gray, Wentai Liu, Thomas A. Hughes, Ralph K. Cavin III, Su-Shing Chen

Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990

The design of a high-performance scalable architecture for image processing applications.

C. Thomas Gray, Wentai Liu, Thomas A. Hughes, Ralph K. Cavin III

Proceedings of the Application Specific Array Processors, 1990