Wentai Liu

According to our database1, Wentai Liu authored at least 103 papers between 1981 and 2019.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2017, "For contributions to electronically-aided neural prosthetic devices".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
A Novel Biomimetic Stimulator System for Neural Implant.
Proceedings of the 2019 9th International IEEE/EMBS Conference on Neural Engineering (NER), 2019

2018
Online Artifact Cancelation in Same-Electrode Neural Stimulation and Recording Using a Combined Hardware and Software Architecture.
IEEE Trans. Biomed. Circuits Syst., 2018

Improving EEG Source Localization with a Novel Regularization: Spatiotemporal Graph Total Variation (STGTV) Method.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018

Impact of Electrode Number on the Performance of High-Definition Transcranial Direct Current Stimulation (HD-tDCS).
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018

A Wireless Platform to Support Pre-Clinical Trial of Neural Implant for Spinal Cord Injury.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018

Current Design with Minimum Error in Transcranial Direct Current Stimulation.
Proceedings of the Brain Informatics - International Conference, 2018

2017
A Fully Integrated Wireless SoC for Motor Function Recovery After Spinal Cord Injury.
IEEE Trans. Biomed. Circuits Syst., 2017

Thermal model of spiked electrode in Transcutaneous Electrical Nerve Stimulation (TENS).
Proceedings of the 8th International IEEE/EMBS Conference on Neural Engineering, 2017

Accelerated high-resolution EEG source imaging.
Proceedings of the 8th International IEEE/EMBS Conference on Neural Engineering, 2017

2016
Introduction to the Special Bio-Section of the 2016 International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2016

22.2 A 176-channel 0.5cm3 0.7g wireless implant for motor function recovery after spinal cord injury.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Phase-amplitude coupling analysis for seizure evolvement using Hilbert Huang Transform.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

Graph fractional-order total variation EEG source reconstruction.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

A hybrid hardware and software approach for cancelling stimulus artifacts during same-electrode neural stimulation and recording.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

2015
Wireless Gigabit Data Telemetry for Large-Scale Neural Recording.
IEEE J. Biomed. Health Informatics, 2015

F3: Cutting the last wire - Advances in wireless power.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
A Frequency Shaping Neural Recorder With 3 pF Input Capacitance and 11 Plus 4.5 Bits Dynamic Range.
IEEE Trans. Biomed. Circuits Syst., 2014

Bio-impedance characterization technique with implantable neural stimulator using biphasic current stimulus.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

Comparison study of seizure detection using stationary and nonstationary methods.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

Design and fabrication of a multi-electrode array for spinal cord epidural stimulation.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

2013
A Fully-Integrated High-Compliance Voltage SoC for Epi-Retinal and Neural Prostheses.
IEEE Trans. Biomed. Circuits Syst., 2013

A 37.6mm<sup>2</sup> 1024-channel high-compliance-voltage SoC for epiretinal prostheses.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
Analysis of Dual Band Power and Data Telemetry for Biomedical Implants.
IEEE Trans. Biomed. Circuits Syst., 2012

Bioelectronics for sustainable healthcare.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Virtual electrode stimulation in a multi-channel stimulation system.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

2011
A 64-channel neuron recording system.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

Analysis and design of data transmission protocol for 1024-channel retinal prosthesis.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

A non-coherent versatile DPSK receiver for high channel-density neural prosthesis.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
An Integrated 256-Channel Epiretinal Prosthesis.
IEEE J. Solid State Circuits, 2010

Engineering hope with biomimetic microelectronic systems.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
Circuit and Coil Design for In-Vitro Magnetic Neural Stimulation Systems.
IEEE Trans. Biomed. Circuits Syst., 2009

Neural signal classification using a simplified feature set with nonparametric clustering.
Neurocomputing, 2009

Noise Characterization, Modeling, and Reduction for In Vivo Neural Recording.
Proceedings of the Advances in Neural Information Processing Systems 22: 23rd Annual Conference on Neural Information Processing Systems 2009. Proceedings of a meeting held 7-10 December 2009, 2009

A biomedical multiprocessor SoC for closed-loop neuroprosthetic applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 220nW Neural Amplifier for Multi-channel Neural Recording Systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

128-channel Spike Sorting Processor with a Parallel-folding Structure in 90nm Process.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

On-chip Principal Component Analysis with a Mean Pre-estimation Method for Spike Sorting.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Closed-loop Eyelid Reanimation System with Real-time Blink Detection and Electrochemical Stimulation for Facial Nerve Paralysis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Evolving Mean Shift with Adaptive Bandwidth: A Fast and Noise Robust Approach.
Proceedings of the Computer Vision, 2009

2008
Integrated VCOs for Medical Implant Transceivers.
VLSI Design, 2008

A Non-Coherent DPSK Data Receiver With Interference Cancellation for Dual-Band Transcutaneous Telemetries.
IEEE J. Solid State Circuits, 2008

Design Optimization for Integrated Neural Recording Systems.
IEEE J. Solid State Circuits, 2008

Spike Feature Extraction Using Informative Samples.
Proceedings of the Advances in Neural Information Processing Systems 21, 2008

A 128-Channel 6mW Wireless Neural Recording IC with On-the-Fly Spike Sorting and UWB Tansmitter.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 4-channel wearable wireless neural recording system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
SOI CMOS Implementation of a Multirate PSK Demodulator for Space Communications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Wireless Body Sensor Network Using Medical Implant Band.
J. Medical Syst., 2007

A MICS Band Wireless Body Sensor Network.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2007

A Non-Coherent PSK Receiver with Interference-Canceling for Transcutaneous Neural Implants.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
A neural recording system for monitoring shark behavior.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Discrete-Time Analysis of an All-Digital and Multirate Symbol Timing Recovery Scheme for Sampling Receivers.
Proceedings of IEEE International Conference on Communications, 2006

Integrated VCO Design for MICS Transceivers.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
A low-power multirate differential PSK receiver for space applications.
IEEE Trans. Veh. Technol., 2005

Design and analysis of an adaptive transcutaneous power telemetry for biomedical implants.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Architecture tradeoffs in high-density microstimulators for retinal prosthesis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

An optimal design methodology for inductive power link with class-E amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Impact of an SoC Research Project on Microelectronics Education: A Case Study.
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

A closed-form delay formula for on-chip RLC interconnects in current-mode signaling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Power supply topologies for biphasic stimulation in inductively powered implants.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Image processing and interface for retinal visual prostheses.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability.
IEEE Trans. Very Large Scale Integr. Syst., 2004

A closed loop transcutaneous power transfer system for implantable devices with enhanced stability.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A matched biphasic microstimulator for an implantable retinal prosthetic device.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An efficient inductive power link design for retinal prosthesis.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Simplified delay design guidelines for on-chip global interconnects.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receivers.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
Current-mode signaling in deep submicrometer global interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Analysis of phase noise due to bang-bang phase detector in PLL-based clock and data recovery circuits.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A 22-mW 435 MHz silicon on insulator CMOS high-gain LNA for subsampling receivers.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A smart bi-directional telemetry unit for retinal prosthetic device.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Accurate delay model and experimental verification for current/voltage mode on-chip interconnects.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Low-power design methodology for an on-chip bus with adaptive bandwidth capability.
Proceedings of the 40th Design Automation Conference, 2003

2001
A multi-gigabit CMOS data recovery circuit using an analog parallel sampling technique.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Integrated parametric timing optimization of digital systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1999
An implantable power and data receiver and neuro-stimulus chip for a retinal prosthesis system.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1997
Clocking Optimization and Distribution in Digital Systems with Scheduled Skews.
J. VLSI Signal Process., 1997

Low power data processing by elimination of redundant computations.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Clock Distribution Using Cooperative Ring Oscillators.
Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997

1996
Simulation of real time image processing: MFA in VLSI.
Proceedings of International Conference on Neural Networks (ICNN'96), 1996

1995
High Speed, Fine Resolution Pattern Generation Using the Matched Delay Technique.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Concurrent timing optimization of latch-based digital systems.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

A technique for high-speed, fine-resolution pattern generation and its CMOS implementation.
Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

1994
Timing constraints for wave-pipelined systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Circuit delay calculation considering data dependent delays.
Integr., 1994

Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits.
Proceedings of the 31st Conference on Design Automation, 1994

1993
A bit-serial VLSI architecture for generating moments in real-time.
IEEE Trans. Syst. Man Cybern., 1993

Optical recognition of handwritten Chinese characters: Advances since 1980.
Pattern Recognit., 1993

1991
Theoretical and Practical Issues in CMOS Wave Pipelining.
Proceedings of the VLSI 91, 1991

1990
Scalable VLSI implementations for neural networks.
J. VLSI Signal Process., 1990

Unconstrained via minimization for topological multilayer routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

P<sup>3</sup>A: a partitionable parallel/pipeline architecture for real-time image processing.
Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990

The design of a high-performance scalable architecture for image processing applications.
Proceedings of the Application Specific Array Processors, 1990

1989
Hamiltonian Cycles in the Shuffle-Exchange Network.
IEEE Trans. Computers, 1989

1988
Design graph search problems with learning: A neural network approach.
Neural Networks, 1988

Rasterization theory, architectures, and implementations for a class of two-dimensional problems.
Integr., 1988

A Hierarchical Sigma-Pi Neural Architecture for Learning Search Algorithms.
Proceedings of the Methodologies for Intelligent Systems, 1988

Exploiting Bit Level Concurrency in Real-Time Geometric Feature Extractions.
Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988

Bit-level concurrency in real-time geometric feature extractions.
Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition, 1988

Software experience with concurrent C and LISP in a distributed system.
Proceedings of the Sixteenth ACM Annual Conference on Computer Science, 1988

1986
Parallel Processing for Quadtree Problems.
Proceedings of the International Conference on Parallel Processing, 1986

1985
The design of a vector-radix 2DFFT chip.
Proceedings of the 7th IEEE Symposium on Computer Arithmetic, 1985

1983
Bounds on the saved area ratio due to PLA folding.
Proceedings of the 20th Design Automation Conference, 1983

1981
Overview of an Arithmetic Design System.
Proceedings of the 18th Design Automation Conference, 1981


  Loading...