Ralph K. Cavin III

According to our database1, Ralph K. Cavin III authored at least 42 papers between 1977 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1988, "For technical contributions in systems and signal processing.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Nurturing the Growth of a National Infrastructure in Emerging Technologies.
Proc. IEEE, 2018

2012
Science and Engineering Beyond Moore's Law.
Proc. IEEE, 2012

Prolog to the Section on Science and Engineering Beyond Moore's Law.
Proc. IEEE, 2012

2010
Memory Devices: Energy-Space-Time Tradeoffs.
Proc. IEEE, 2010

Regional, National, and International Nanoelectronics Research Programs: Topical Concentration and Gaps.
Proc. IEEE, 2010

Nanoelectronics Research for Beyond CMOS Information Processing.
Proc. IEEE, 2010

Device and Architecture Outlook for Beyond CMOS Switches.
Proc. IEEE, 2010

2009
Scaling beyond CMOS: Turing-Heisenberg Rapproachment.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
An Assessment of Integrated Digital Cellular Automata Architectures.
Computer, 2008

Emerging Nanoscale Memory and Logic Devices: A Critical Assessment.
Computer, 2008

Emerging Research Architectures.
Computer, 2008

Boolean Logic and Alternative Information-Processing Devices.
Computer, 2008

The Viability of Cellular Automata Architectures for General Purpose Computing.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

2004
A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability.
IEEE Trans. Very Large Scale Integr. Syst., 2004

2003
Current-mode signaling in deep submicrometer global interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2003

A semiconductor industry perspective on future directions in ECE education.
IEEE Trans. Educ., 2003

Limits to binary logic switch scaling - a gedanken model.
Proc. IEEE, 2003

Accurate delay model and experimental verification for current/voltage mode on-chip interconnects.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Low-power design methodology for an on-chip bus with adaptive bandwidth capability.
Proceedings of the 40th Design Automation Conference, 2003

2000
Integrated parametric timing optimization of digital systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1997
Clocking Optimization and Distribution in Digital Systems with Scheduled Skews.
J. VLSI Signal Process., 1997

1995
High Speed, Fine Resolution Pattern Generation Using the Matched Delay Technique.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Concurrent timing optimization of latch-based digital systems.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

A technique for high-speed, fine-resolution pattern generation and its CMOS implementation.
Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

1994
Timing constraints for wave-pipelined systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Circuit delay calculation considering data dependent delays.
Integr., 1994

1993
A bit-serial VLSI architecture for generating moments in real-time.
IEEE Trans. Syst. Man Cybern., 1993

1991
Theoretical and Practical Issues in CMOS Wave Pipelining.
Proceedings of the VLSI 91, 1991

1990
P<sup>3</sup>A: a partitionable parallel/pipeline architecture for real-time image processing.
Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990

The design of a high-performance scalable architecture for image processing applications.
Proceedings of the Application Specific Array Processors, 1990

1989
Hamiltonian Cycles in the Shuffle-Exchange Network.
IEEE Trans. Computers, 1989

1988
Rasterization theory, architectures, and implementations for a class of two-dimensional problems.
Integr., 1988

Exploiting Bit Level Concurrency in Real-Time Geometric Feature Extractions.
Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988

Bit-level concurrency in real-time geometric feature extractions.
Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition, 1988

1984
The Impact of ICs on Computer Technology.
Computer, 1984

Introduction to the SRC design sciences program.
Proceedings of the 21st Design Automation Conference, 1984

1983
Microelectronic architectures and devices for signal and symbol processing.
Integr., 1983

1982
Analysis of error-gradient adaptive linear estimators for a class of stationary dependent processes.
IEEE Trans. Inf. Theory, 1982

1980
An Efficient Computational Procedure for the Evaluation of the M/M/I Transient State Occupancy Probabilities.
IEEE Trans. Commun., 1980

1977
On the Maximum Average Throughput Rate for a Tandem Node Network.
IEEE Trans. Commun., 1977

Dynamic Modeling and Control of Digital Communication Networks.
Computer, 1977

Distributed parameter system optimum control design via finite element discretization.
Autom., 1977


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