Ralph K. Cavin III

Paolo Lugli

Proc. IEEE, 2012

Prolog to the Section on Science and Engineering Beyond Moore's Law.

[BibT_eX]

[DOI]

Paolo Lugli

Proc. IEEE, 2012

2010

Memory Devices: Energy-Space-Time Tradeoffs.

[BibT_eX]

[DOI]

Proc. IEEE, 2010

Regional, National, and International Nanoelectronics Research Programs: Topical Concentration and Gaps.

[BibT_eX]

[DOI]

Proc. IEEE, 2010

Nanoelectronics Research for Beyond CMOS Information Processing.

[BibT_eX]

[DOI]

Proc. IEEE, 2010

Device and Architecture Outlook for Beyond CMOS Switches.

[BibT_eX]

[DOI]

Proc. IEEE, 2010

2009

Scaling beyond CMOS: Turing-Heisenberg Rapproachment.

[BibT_eX]

[DOI]

Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008

An Assessment of Integrated Digital Cellular Automata Architectures.

[BibT_eX]

[DOI]

Computer, 2008

Emerging Nanoscale Memory and Logic Devices: A Critical Assessment.

[BibT_eX]

[DOI]

Computer, 2008

Emerging Research Architectures.

[BibT_eX]

[DOI]

Computer, 2008

Boolean Logic and Alternative Information-Processing Devices.

[BibT_eX]

[DOI]

Computer, 2008

The Viability of Cellular Automata Architectures for General Purpose Computing.

[BibT_eX]

Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

2006

A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2006

2005

Future devices for information processing.

[BibT_eX]

[DOI]

Proceedings of the 31st European Solid-State Circuits Conference, 2005

2004

A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

2003

Current-mode signaling in deep submicrometer global interconnects.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

A semiconductor industry perspective on future directions in ECE education.

[BibT_eX]

[DOI]

William H. Joyner Jr.

Virginia C. Wiggins

IEEE Trans. Educ., 2003

Limits to binary logic switch scaling - a gedanken model.

[BibT_eX]

[DOI]

Proc. IEEE, 2003

Accurate delay model and experimental verification for current/voltage mode on-chip interconnects.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Low-power design methodology for an on-chip bus with adaptive bandwidth capability.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

2002

Delay and power model for current-mode signaling in deep submicron global interconnects.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2000

Integrated parametric timing optimization of digital systems.

[BibT_eX]

[DOI]

Hong-Yean Hsieh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1997

Clocking Optimization and Distribution in Digital Systems with Scheduled Skews.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1997

The delay vernier pattern generation technique.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1997

A CMOS high-speed data recovery circuit using the matched delay sampling technique.

[BibT_eX]

[DOI]

Jin-Ku Kang

IEEE J. Solid State Circuits, 1997

1995

High Speed, Fine Resolution Pattern Generation Using the Matched Delay Technique.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Concurrent timing optimization of latch-based digital systems.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

A technique for high-speed, fine-resolution pattern generation and its CMOS implementation.

[BibT_eX]

[DOI]

Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

1994

A 250-MHz wave pipelined adder in 2-μm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, September, 1994

A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution.

[BibT_eX]

[DOI]

C. Thomas Gray

Wilhelmus A. M. Van Noije

Thomas A. Hughes

IEEE J. Solid State Circuits, March, 1994

Timing constraints for wave-pipelined systems.

[BibT_eX]

[DOI]

C. Thomas Gray

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Circuit delay calculation considering data dependent delays.

[BibT_eX]

[DOI]

Integr., 1994

1993

A bit-serial VLSI architecture for generating moments in real-time.

[BibT_eX]

[DOI]

Su-Shing Chen

IEEE Trans. Syst. Man Cybern., 1993

1991

Theoretical and Practical Issues in CMOS Wave Pipelining.

[BibT_eX]

Proceedings of the VLSI 91, 1991

1990

Design of integrated circuits: directions and challenges.

[BibT_eX]

[DOI]

Jeffrey L. Hilbert

Proc. IEEE, 1990

P<sup>3</sup>A: a partitionable parallel/pipeline architecture for real-time image processing.

[BibT_eX]

[DOI]

Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990

The design of a high-performance scalable architecture for image processing applications.

[BibT_eX]

[DOI]

Proceedings of the Application Specific Array Processors, 1990

1989

Hamiltonian Cycles in the Shuffle-Exchange Network.

[BibT_eX]

[DOI]

Thomas H. Hildebrandt

IEEE Trans. Computers, 1989

The Semiconductor Research Corporation: Cooperative research.

[BibT_eX]

[DOI]

Larry W. Sumney

Robert M. Burger

Proc. IEEE, 1989

1988

Rasterization theory, architectures, and implementations for a class of two-dimensional problems.

[BibT_eX]

[DOI]

Integr., 1988

Exploiting Bit Level Concurrency in Real-Time Geometric Feature Extractions.

[BibT_eX]

[DOI]

Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988

Bit-level concurrency in real-time geometric feature extractions.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition, 1988

1986

A perspective on CMOS technology trends.

[BibT_eX]

[DOI]

William C. Holton

Proc. IEEE, 1986

1984

The Impact of ICs on Computer Technology.

[BibT_eX]

[DOI]

Computer, 1984

Introduction to the SRC design sciences program.

[BibT_eX]

[DOI]

Proceedings of the 21st Design Automation Conference, 1984

1983

Microelectronic architectures and devices for signal and symbol processing.

[BibT_eX]

[DOI]

Noel R. Strader

Integr., 1983

1982

Analysis of error-gradient adaptive linear estimators for a class of stationary dependent processes.

[BibT_eX]

[DOI]

William M. Reed

IEEE Trans. Inf. Theory, 1982

1980

An Efficient Computational Procedure for the Evaluation of the M/M/I Transient State Occupancy Probabilities.

[BibT_eX]

[DOI]

Donald A. Johnston

IEEE Trans. Commun., 1980

1977

On the Maximum Average Throughput Rate for a Tandem Node Network.

[BibT_eX]

[DOI]

J. N. Holyoak

IEEE Trans. Commun., 1977

Dynamic Modeling and Control of Digital Communication Networks.

[BibT_eX]

[DOI]

Computer, 1977

Distributed parameter system optimum control design via finite element discretization.

[BibT_eX]

[DOI]