Thomas J. Repetti
According to our database1, Thomas J. Repetti authored at least 4 papers between 2017 and 2020.
Legend:Book In proceedings Article PhD thesis Other
Catena: A Near-Threshold, Sub-0.4-mW, 16-Core Programmable Spatial Array Accelerator for the Ultralow-Power Mobile and Embedded Internet of Things.
IEEE J. Solid State Circuits, 2020
Catena: A 0.5-V Sub-0.4-mW 16-Core Spatial Array Accelerator for Mobile and Embedded Computing.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Master of none acceleration: a comparison of accelerator architectures for analytical query processing.
Proceedings of the 46th International Symposium on Computer Architecture, 2019
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017