Joao Pedro Cerqueira

According to our database1, Joao Pedro Cerqueira authored at least 16 papers between 2012 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


Online presence:



Catena: A Near-Threshold, Sub-0.4-mW, 16-Core Programmable Spatial Array Accelerator for the Ultralow-Power Mobile and Embedded Internet of Things.
IEEE J. Solid State Circuits, 2020

Always-On, Sub-300-nW, Event-Driven Spiking Neural Network based on Spike-Driven Clock-Generation and Clock- and Power-Gating for an Ultra-Low-Power Intelligent Device.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020

A Near-Threshold Spiking Neural Network Accelerator With a Body-Swapping-Based In Situ Error Detection and Correction Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Design of an Always-On Deep Neural Network-Based 1- $\mu$ W Voice Activity Detector Aided With a Customized Software Model for Analog Feature Extraction.
IEEE J. Solid State Circuits, 2019

Catena: A 0.5-V Sub-0.4-mW 16-Core Spatial Array Accelerator for Mobile and Embedded Computing.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A Femto/Pico-Watt Feedforward Leakage Self-Suppression Logic Family in 180 nm to 28 nm Technologies.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Master of none acceleration: a comparison of accelerator architectures for analytical query processing.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

A 1μW voice activity detector using analog feature extraction and digital deep neural network.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Temporarily Fine-Grained Sleep Technique for Near- and Subthreshold Parallel Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Pipelining a triggered processing element.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Near-Vt adaptive microprocessor and power-management-unit system based on direct error regulation.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

A 0.17-mm<sup>2</sup> 3.19-nJ/transform 256-point fast fourier transform core based on spatiotemporally fine-grained active leakage suppression.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

A 450mV timing-margin-free waveform sorter based on body swapping error correction.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

1.74-µW/ch, 95.3%-accurate spike-sorting hardware based on Bayesian decision.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Design of a low-power adaptive LMS equalizer for hearing-aid applications.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

JCHAI3D - Multiplatform Framework for Healthcare Applications: Multiplatform Framework for Graphic and Haptic Processing Develop in Java.
Proceedings of the 14th Symposium on Virtual and Augmented Reality, 2012